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-rw-r--r--src/mainboard/amd/dbm690t/romstage.c2
-rw-r--r--src/mainboard/amd/pistachio/romstage.c2
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c2
-rw-r--r--src/mainboard/asus/a8n_e/romstage.c3
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c4
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c2
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c2
-rw-r--r--src/mainboard/msi/ms7135/romstage.c3
-rw-r--r--src/mainboard/msi/ms7260/romstage.c1
-rw-r--r--src/mainboard/msi/ms9185/romstage.c2
-rw-r--r--src/mainboard/msi/ms9282/romstage.c2
11 files changed, 4 insertions, 21 deletions
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index c83759bbad..697319356f 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -57,7 +57,6 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -67,6 +66,7 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 2e5c4a0812..d440f4d2f9 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -51,7 +51,6 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -61,6 +60,7 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 67c7dbf551..82a404b50b 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -29,8 +29,6 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
-#define DEBUG_SMBUS 1
-
#define SET_NB_CFG_54 1
//used by raminit
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 8e0ba2925e..ae70c847f3 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -30,9 +30,6 @@
/* Used by raminit. */
#define QRANK_DIMM_SUPPORT 1
-/* Turn this on for SMBus debugging output. */
-#define DEBUG_SMBUS 0
-
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 4ec3aee813..b6c3c3f686 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -40,8 +40,6 @@ unsigned int get_sbdn(unsigned bus);
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
-/* #define DEBUG_SMBUS 1 */
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -59,10 +57,10 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 13101b0217..4f4b481b8a 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -44,8 +44,6 @@ unsigned int get_sbdn(unsigned bus);
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-/* #define DEBUG_SMBUS 1 */
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 43c9b20bad..6ea41b6e4b 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -445,7 +445,7 @@ void real_main(unsigned long bist)
#if !CONFIG_HAVE_ACPI_RESUME
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
sdram_dump_mchbar_registers();
#endif
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 6616dc1444..9477c6e514 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -30,9 +30,6 @@
/* Used by raminit. */
#define QRANK_DIMM_SUPPORT 1
-/* Turn this on for SMBus debugging output. */
-#define DEBUG_SMBUS 0
-
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 7a8bf13a79..a8697b5114 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -24,7 +24,6 @@
#define __PRE_RAM__
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
-// #define DEBUG_SMBUS 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 255815707a..4903b3edd7 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -42,8 +42,6 @@
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
-#define DEBUG_SMBUS 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 11c92b81fa..b552788a54 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -38,8 +38,6 @@
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
-#define DEBUG_SMBUS 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>