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-rw-r--r--src/mainboard/advansus/a785e-i/Makefile.inc4
-rw-r--r--src/mainboard/asus/m5a88-v/Makefile.inc4
-rw-r--r--src/mainboard/avalue/eax-785e/Makefile.inc4
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h2
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index 45c257ad24..7b6a8e6ce5 100644
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -2,8 +2,8 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
- romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc
index 45c257ad24..7b6a8e6ce5 100644
--- a/src/mainboard/asus/m5a88-v/Makefile.inc
+++ b/src/mainboard/asus/m5a88-v/Makefile.inc
@@ -2,8 +2,8 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
- romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc
index 45c257ad24..7b6a8e6ce5 100644
--- a/src/mainboard/avalue/eax-785e/Makefile.inc
+++ b/src/mainboard/avalue/eax-785e/Makefile.inc
@@ -2,8 +2,8 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
- romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 038ad8b0ec..37caa6ef45 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -16,7 +16,7 @@
#include "AGESA.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <Lib/amdlib.h>
+#include <amdlib.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index d0a989277e..a91bd0f2c2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -18,7 +18,7 @@
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f14/AGESA.h>
-#include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
+#include <amdlib.h>
/**
* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)