diff options
Diffstat (limited to 'src/mainboard')
402 files changed, 10974 insertions, 10974 deletions
diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb index 843728dc20..7d9b82ba1a 100644 --- a/src/mainboard/a-trend/atc-6220/Config.lb +++ b/src/mainboard/a-trend/atc-6220/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/a-trend/atc-6220/Options.lb +++ b/src/mainboard/a-trend/atc-6220/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/a-trend/atc-6220/auto.c b/src/mainboard/a-trend/atc-6220/auto.c index 2e60b1c526..1b5891e519 100644 --- a/src/mainboard/a-trend/atc-6220/auto.c +++ b/src/mainboard/a-trend/atc-6220/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/a-trend/atc-6220/irq_tables.c b/src/mainboard/a-trend/atc-6220/irq_tables.c index e13fb52e43..8415fb12c3 100644 --- a/src/mainboard/a-trend/atc-6220/irq_tables.c +++ b/src/mainboard/a-trend/atc-6220/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x600, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb index f3e10c8ce8..dd7ee2df9b 100644 --- a/src/mainboard/a-trend/atc-6240/Config.lb +++ b/src/mainboard/a-trend/atc-6240/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/a-trend/atc-6240/Options.lb b/src/mainboard/a-trend/atc-6240/Options.lb index 31c70358f5..feb32318c7 100644 --- a/src/mainboard/a-trend/atc-6240/Options.lb +++ b/src/mainboard/a-trend/atc-6240/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/a-trend/atc-6240/auto.c b/src/mainboard/a-trend/atc-6240/auto.c index eaa8407583..782e307d99 100644 --- a/src/mainboard/a-trend/atc-6240/auto.c +++ b/src/mainboard/a-trend/atc-6240/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/a-trend/atc-6240/irq_tables.c b/src/mainboard/a-trend/atc-6240/irq_tables.c index 0e4c167866..63b276f4fe 100644 --- a/src/mainboard/a-trend/atc-6240/irq_tables.c +++ b/src/mainboard/a-trend/atc-6240/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb index 97c403ce81..d8c1ce3f94 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Config.lb +++ b/src/mainboard/abit/be6-ii_v2_0/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/abit/be6-ii_v2_0/Options.lb b/src/mainboard/abit/be6-ii_v2_0/Options.lb index 986b770bbc..55255c120e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Options.lb +++ b/src/mainboard/abit/be6-ii_v2_0/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb. +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. diff --git a/src/mainboard/abit/be6-ii_v2_0/auto.c b/src/mainboard/abit/be6-ii_v2_0/auto.c index dd43c07a84..fe9bce8423 100644 --- a/src/mainboard/abit/be6-ii_v2_0/auto.c +++ b/src/mainboard/abit/be6-ii_v2_0/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c index 88aaf9c885..c33e0331f7 100644 --- a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c +++ b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x1c20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb index 8906f6e191..3437d74b3f 100644 --- a/src/mainboard/advantech/pcm-5820/Config.lb +++ b/src/mainboard/advantech/pcm-5820/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb index 8e8d078aaa..43bbd6b3dd 100644 --- a/src/mainboard/advantech/pcm-5820/Options.lb +++ b/src/mainboard/advantech/pcm-5820/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default PIRQ_ROUTE = 1 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_OPTION_TABLE = 0 -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # # CBFS diff --git a/src/mainboard/advantech/pcm-5820/auto.c b/src/mainboard/advantech/pcm-5820/auto.c index bcb65c245d..20dff7eedb 100644 --- a/src/mainboard/advantech/pcm-5820/auto.c +++ b/src/mainboard/advantech/pcm-5820/auto.c @@ -36,7 +36,7 @@ static void main(unsigned long bist) { - w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/advantech/pcm-5820/irq_tables.c b/src/mainboard/advantech/pcm-5820/irq_tables.c index 573ecd7d44..d176ecbf26 100644 --- a/src/mainboard/advantech/pcm-5820/irq_tables.c +++ b/src/mainboard/advantech/pcm-5820/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x12 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb index 90525f32b0..c82c664a7c 100644 --- a/src/mainboard/amd/db800/Config.lb +++ b/src/mainboard/amd/db800/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,14 +14,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb index 33d1d15295..06a0e386ce 100644 --- a/src/mainboard/amd/db800/Options.lb +++ b/src/mainboard/amd/db800/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=4 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=4 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/db800/cache_as_ram_auto.c b/src/mainboard/amd/db800/cache_as_ram_auto.c index c0554f1f9e..0ea76445aa 100644 --- a/src/mainboard/amd/db800/cache_as_ram_auto.c +++ b/src/mainboard/amd/db800/cache_as_ram_auto.c @@ -113,7 +113,7 @@ void cache_as_ram_main(void) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c index f9a6312fa8..c2c154ecda 100644 --- a/src/mainboard/amd/db800/irq_tables.c +++ b/src/mainboard/amd/db800/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb index 0735c03a32..9a3b6d93ad 100644 --- a/src/mainboard/amd/dbm690t/Config.lb +++ b/src/mainboard/amd/dbm690t/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb index be32edf8a1..8835d2997d 100644 --- a/src/mainboard/amd/dbm690t/Options.lb +++ b/src/mainboard/amd/dbm690t/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="dbm690t" -default MAINBOARD_VENDOR="amd" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="dbm690t" +default CONFIG_MAINBOARD_VENDOR="amd" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -284,21 +284,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb # diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 9aaede4b8d..3829a7a082 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c index 29cdfb37f7..75ff96c338 100644 --- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -100,7 +100,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -139,14 +139,14 @@ normal_image: fallback_image: post_code(0x25); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -159,7 +159,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { @@ -170,7 +170,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, TTYS0_BASE); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 4f5bec3273..daaf4d2daa 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb index 7a6ff1e54f..a92120e7c9 100644 --- a/src/mainboard/amd/norwich/Config.lb +++ b/src/mainboard/amd/norwich/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,7 +14,7 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end @@ -22,8 +22,8 @@ end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -39,7 +39,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb index 634f848c5f..fc71fdb24c 100644 --- a/src/mainboard/amd/norwich/Options.lb +++ b/src/mainboard/amd/norwich/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c index 5e408b7241..5279bcd27e 100644 --- a/src/mainboard/amd/norwich/irq_tables.c +++ b/src/mainboard/amd/norwich/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 90d840316c..33079a2607 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb index 29e7802e25..321c4d292d 100644 --- a/src/mainboard/amd/pistachio/Options.lb +++ b/src/mainboard/amd/pistachio/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="pistachio" -default MAINBOARD_VENDOR="amd" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="pistachio" +default CONFIG_MAINBOARD_VENDOR="amd" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -284,21 +284,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb # diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 541f6e48f6..e985d4552a 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c index ade2024355..bbe96ce978 100644 --- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -94,7 +94,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -133,14 +133,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) fallback_image: post_code(0x02); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -154,8 +154,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = - (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - - DCACHE_RAM_GLOBAL_VAR_SIZE); + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index f0f77ef37c..23b38ca846 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb index 426b7a62c7..466703fcc3 100644 --- a/src/mainboard/amd/rumba/Config.lb +++ b/src/mainboard/amd/rumba/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb index 70c05bfa56..eff01c1087 100644 --- a/src/mainboard/amd/rumba/Options.lb +++ b/src/mainboard/amd/rumba/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -125,21 +125,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -151,13 +151,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c index b3a9b839ee..e1326ff622 100644 --- a/src/mainboard/amd/rumba/auto.c +++ b/src/mainboard/amd/rumba/auto.c @@ -127,7 +127,7 @@ static void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb index 85d61720bc..80d6318792 100644 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -15,25 +15,25 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -#if HAVE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES # object acpi_tables.o # object fadt.o -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object dsdt_bus0.o # else # object dsdt.o # end # object ssdt.o -# if ACPI_SSDTX_NUM -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_ACPI_SSDTX_NUM +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object ssdt2_bus0.o # else # object ssdt2.o @@ -41,36 +41,36 @@ end # end #end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end @@ -81,26 +81,26 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -110,13 +110,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -134,8 +134,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -143,7 +143,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -168,12 +168,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb index 697e9119a2..68d3f10b2f 100644 --- a/src/mainboard/amd/serengeti_cheetah/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -1,85 +1,85 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=1 +default CONFIG_ACPI_SSDTX_NUM=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=8 default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -207,10 +207,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 @@ -218,8 +218,8 @@ default CONFIG_USE_INIT=0 ## for rev F training on AP purpose ## default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -229,37 +229,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="serengeti_cheetah" -default MAINBOARD_VENDOR="AMD" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah" +default CONFIG_MAINBOARD_VENDOR="AMD" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -273,8 +273,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -290,21 +290,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -316,17 +316,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index d671907687..04e52364de 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -39,7 +39,7 @@ static void dump_mem(unsigned start, unsigned end) #endif extern unsigned char AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern unsigned char AmlCode_ssdt2[]; extern unsigned char AmlCode_ssdt3[]; extern unsigned char AmlCode_ssdt4[]; @@ -263,7 +263,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c index 584309508e..5a173e006b 100644 --- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -74,8 +74,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c index 95a3395abe..fb1be8dd28 100644 --- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -45,7 +45,7 @@ static void post_code(uint8_t value) { #endif } #endif -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -59,7 +59,7 @@ static void post_code(uint8_t value) { #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -201,7 +201,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -215,21 +215,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -253,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -265,11 +265,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -284,7 +284,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f1b374ae95..cd580f1232 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -109,7 +109,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -132,7 +132,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb index 405ebcf4ff..456ad0ecfd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -17,8 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,51 +33,51 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -88,27 +88,27 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -118,13 +118,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -177,12 +177,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index c62fbe273e..cd5f586ca7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -17,126 +17,126 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK -uses PCI_BUS_SEGN_BITS +uses CONFIG_PCI_BUS_SEGN_BITS uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CAR_FAM10 -uses AMD_UCODE_PATCH_FILE +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 +default CONFIG_ROM_SIZE=1024*1024 ## ## #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 1024K - 8K -default FALLBACK_SIZE=0xFE000 +default CONFIG_FALLBACK_SIZE=0xFE000 #FAILOVER: 8k -default FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. @@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=31 +default CONFIG_ACPI_SSDTX_NUM=31 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -190,58 +190,58 @@ default CONFIG_MAX_PHYSICAL_CPUS=8 default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x00 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 #it only be 0, 1, 2, 3, 4 and default is 0 -#default PCI_BUS_SEGN_BITS=3 +#default CONFIG_PCI_BUS_SEGN_BITS=3 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 default CONFIG_USE_INIT=0 #default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 default CONFIG_AMDMCT = 1 @@ -253,10 +253,10 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Cheetah Fam10" -default MAINBOARD_VENDOR="AMD" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10" +default CONFIG_MAINBOARD_VENDOR="AMD" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## ## Set microcode patch file name @@ -266,34 +266,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" ## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 768k heap ## -default HEAP_SIZE=0xc0000 +default CONFIG_HEAP_SIZE=0xc0000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00200000 +default CONFIG_RAMBASE=0x00200000 ## ## Load the payload from the ROM @@ -307,8 +307,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -325,21 +325,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -351,17 +351,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index ed53938a63..8239a115bf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -49,7 +49,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; extern u8 AmlCode_ssdt[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) printk_debug("ACPI: * SSDT for PState at %lx\n", current); current = acpi_add_ssdt_pstates(rsdt, current); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index 49dadd799a..fbb8c14388 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -50,9 +50,9 @@ #include "lib/delay.c" #if NODE_NUMS == 64 - #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn)) + #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn)) #else - #define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn) + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn) #endif //#include "cpu/x86/lapic/boot_cpu.c" @@ -73,8 +73,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c index 38196b262e..4e484553f7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -60,7 +60,7 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "ram/ramtest.c" @@ -80,7 +80,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #include "cpu/x86/bist.h" -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -142,10 +142,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (USE_FAILOVER_IMAGE == 0) */ +#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -190,7 +190,7 @@ normal_image: ); fallback_image: - #if HAVE_FAILOVER_BOOT==1 + #if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -198,22 +198,22 @@ fallback_image: #endif ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0. -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#if (USE_FAILOVER_IMAGE==0) +#if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -229,7 +229,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; msr_t msr; @@ -243,12 +243,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk_debug("\n"); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -380,4 +380,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#endif /* USE_FAILOVER_IMAGE==0 */ +#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index d1d1ff8e32..de8eacde6b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -116,11 +116,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) } -#if CBB - write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if(sysconf.nodes>32) { - write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 04698d7369..25093fd8b1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ static void setup_mb_resource_map(void) * This field defines the upp adddress bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index d25ea1608b..89174f1a2a 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -13,21 +13,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -55,7 +55,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb index 24fff9b1ac..6f83531541 100644 --- a/src/mainboard/arima/hdama/Options.lb +++ b/src/mainboard/arima/hdama/Options.lb @@ -1,61 +1,61 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_LOGICAL_CPUS -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -69,48 +69,48 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_LOGICAL_CPUS=1 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -128,9 +128,9 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 #VGA @@ -140,38 +140,38 @@ default CONFIG_PCI_ROM_RUN=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="HDAMA" -default MAINBOARD_VENDOR="ARIMA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +default CONFIG_MAINBOARD_VENDOR="ARIMA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -185,8 +185,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -203,21 +203,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -229,17 +229,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/arima/hdama/cache_as_ram_auto.c b/src/mainboard/arima/hdama/cache_as_ram_auto.c index fe19502543..a9a8a79333 100644 --- a/src/mainboard/arima/hdama/cache_as_ram_auto.c +++ b/src/mainboard/arima/hdama/cache_as_ram_auto.c @@ -96,7 +96,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -148,7 +148,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -186,7 +186,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index add22b4e03..2ca98066d0 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb index e00c21f5f3..41c77e0243 100644 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ b/src/mainboard/artecgroup/dbe61/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,13 +14,13 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -36,7 +36,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb index 8ac10de49e..3fa9ae27ce 100644 --- a/src/mainboard/artecgroup/dbe61/Options.lb +++ b/src/mainboard/artecgroup/dbe61/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_VIDEO_MB=8 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=3 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=3 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c index b42c4b514e..87931ae3c5 100644 --- a/src/mainboard/artecgroup/dbe61/irq_tables.c +++ b/src/mainboard/artecgroup/dbe61/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb index 9f66182167..08010fa236 100644 --- a/src/mainboard/asi/mb_5blgp/Config.lb +++ b/src/mainboard/asi/mb_5blgp/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asi/mb_5blgp/Options.lb b/src/mainboard/asi/mb_5blgp/Options.lb index 870f3b80f9..f5854b3b7f 100644 --- a/src/mainboard/asi/mb_5blgp/Options.lb +++ b/src/mainboard/asi/mb_5blgp/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default PIRQ_ROUTE = 1 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_OPTION_TABLE = 0 -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # # CBFS diff --git a/src/mainboard/asi/mb_5blgp/auto.c b/src/mainboard/asi/mb_5blgp/auto.c index 962691d8ac..60c8dd7c1a 100644 --- a/src/mainboard/asi/mb_5blgp/auto.c +++ b/src/mainboard/asi/mb_5blgp/auto.c @@ -36,7 +36,7 @@ static void main(unsigned long bist) { - pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asi/mb_5blgp/irq_tables.c b/src/mainboard/asi/mb_5blgp/irq_tables.c index fe39ee86bf..79e9a88332 100644 --- a/src/mainboard/asi/mb_5blgp/irq_tables.c +++ b/src/mainboard/asi/mb_5blgp/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x12 << 3) | 0x0, /* Interrupt router device */ 0x8800, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb index 6697a42bfa..f0008f7a65 100644 --- a/src/mainboard/asi/mb_5blmp/Config.lb +++ b/src/mainboard/asi/mb_5blmp/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,7 +14,7 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end @@ -22,22 +22,22 @@ end ## Romcc output ## # makerule ./failover.E -# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end # # makerule ./failover.inc -# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -51,7 +51,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -73,7 +73,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -# if USE_FALLBACK_IMAGE +# if CONFIG_USE_FALLBACK_IMAGE # ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc # end diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb index c1ea8c4e24..de9cd83c43 100644 --- a/src/mainboard/asi/mb_5blmp/Options.lb +++ b/src/mainboard/asi/mb_5blmp/Options.lb @@ -1,52 +1,52 @@ -uses HAVE_PIRQ_TABLE +uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_CBFS -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 # uses CONFIG_CONSOLE_VGA # uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256 * 1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256 * 1024 ### ### Build options @@ -55,12 +55,12 @@ default ROM_SIZE = 256 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -70,49 +70,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 # TODO? -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 # TODO? +default CONFIG_PIRQ_ROUTE=1 ## ## Build code to export a CMOS option table ## -# default HAVE_OPTION_TABLE=0 +# default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -# default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +# default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -122,21 +122,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -148,13 +148,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 # VGA Console # default CONFIG_CONSOLE_VGA=1 diff --git a/src/mainboard/asi/mb_5blmp/auto.c b/src/mainboard/asi/mb_5blmp/auto.c index 8e8b61c717..a98d640acc 100644 --- a/src/mainboard/asi/mb_5blmp/auto.c +++ b/src/mainboard/asi/mb_5blmp/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb index 065a7ab7cb..72380d9e8a 100644 --- a/src/mainboard/asus/a8n_e/Config.lb +++ b/src/mainboard/asus/a8n_e/Config.lb @@ -21,36 +21,36 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -60,8 +60,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -69,7 +69,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,24 +81,24 @@ end mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds # ROMSTRAP table for CK804. -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end end mainboardinit cpu/amd/car/cache_as_ram.inc -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index 5f4c65715e..4682869577 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -19,153 +19,153 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 252 * 1024 -default FAILOVER_SIZE = 4 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_FAILOVER_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 13 -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 252 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 13 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 1 # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 # SMP support (only worry about 2 micro processors). default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 # 1G memory hole. -default HW_MEM_HOLE_SIZEK = 0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x10 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 # Make the SB HT chain on bus 0, default is not (0). -default SB_HT_CHAIN_ON_BUS0 = 2 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 # default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console default CONFIG_CONSOLE_VGA = 1 # For VGA console default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 32 * 1024 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 default CONFIG_USE_INIT = 0 default CONFIG_AP_CODE_IN_CAR = 0 -default MEM_TRAIN_SEQ = 2 -default WAIT_BEFORE_CPUS_INIT = 0 -# default ENABLE_APIC_EXT_ID = 0 -# default APIC_ID_OFFSET = 0x10 -# default LIFT_BSP_APIC_ID = 0 +default CONFIG_MEM_TRAIN_SEQ = 2 +default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 +# default CONFIG_ENABLE_APIC_EXT_ID = 0 +# default CONFIG_APIC_ID_OFFSET = 0x10 +# default CONFIG_LIFT_BSP_APIC_ID = 0 # default CONFIG_PCI_64BIT_PREF_MEM = 1 default CONFIG_IOAPIC = 1 -default MAINBOARD_PART_NUMBER = "A8N-E" -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 +default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 # Only use the option table in a normal image. -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) -default _RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c index 1e02e6e0be..a45d8d7966 100644 --- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck894_early_setup(). */ #define CK804_NUM 1 @@ -99,10 +99,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -166,7 +166,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -175,27 +175,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -266,4 +266,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb index a53b262d16..242c104eac 100644 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ b/src/mainboard/asus/a8v-e_se/Config.lb @@ -20,42 +20,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -71,7 +71,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,7 +81,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb index a471b418b2..75c404dd92 100644 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ b/src/mainboard/asus/a8v-e_se/Options.lb @@ -17,156 +17,156 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE # uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "A8V-E SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default ROM_IMAGE_SIZE = 64 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. # default CONFIG_LB_MEM_TOPK = 2048 -default _RAMBASE = 0x00004000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x00004000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index 0a8ca60a8b..b76d011910 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -178,7 +178,7 @@ void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); } -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -187,7 +187,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) unsigned last_boot_normal_x = 1; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); @@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -251,11 +251,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb index 76935320f0..c7f7d6e51a 100644 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ b/src/mainboard/asus/m2v-mx_se/Config.lb @@ -20,18 +20,18 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -39,19 +39,19 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 8f388d5219..d1a08e2c7f 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -17,159 +17,159 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_MAINBOARD_RESOURCES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 0 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 -default HAVE_MAINBOARD_RESOURCES = 1 -default HAVE_LOW_TABLES = 0 -default HAVE_ACPI_RESUME = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 +default CONFIG_HAVE_LOW_TABLES = 0 +default CONFIG_HAVE_ACPI_RESUME = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "M2V-MX SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. default CONFIG_LB_MEM_TOPK = 32768 # to 1MB -default _RAMBASE = 0x1F00000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x1F00000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c index 15dcda5ec1..e5d18e1c94 100644 --- a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); /* If we want to wait for core1 done before DQS training, set it to 0. */ #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -183,12 +183,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; u8 reg; sio_init(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); uart_init(); diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index f6bf656e50..c68fe6174b 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -25,11 +25,11 @@ int add_mainboard_resources(struct lb_memory *mem) { -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - _RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE)); + CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE)); lb_add_memory_range(mem, LB_MEM_RESERVED, - DCACHE_RAM_BASE, DCACHE_RAM_SIZE); + CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); #endif return 0; } diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb index 76ddff64a8..c6486831df 100644 --- a/src/mainboard/asus/mew-am/Config.lb +++ b/src/mainboard/asus/mew-am/Config.lb @@ -18,40 +18,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb index 95be45a13d..c0837b2dda 100644 --- a/src/mainboard/asus/mew-am/Options.lb +++ b/src/mainboard/asus/mew-am/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. diff --git a/src/mainboard/asus/mew-am/auto.c b/src/mainboard/asus/mew-am/auto.c index ea09d6c371..05a163d779 100644 --- a/src/mainboard/asus/mew-am/auto.c +++ b/src/mainboard/asus/mew-am/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c index 84d738dd2d..e07ee20b96 100644 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ b/src/mainboard/asus/mew-am/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index 44439707dd..60f4e152b6 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb index fa0eedc074..71f854d127 100644 --- a/src/mainboard/asus/mew-vm/Options.lb +++ b/src/mainboard/asus/mew-vm/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_IDE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -53,28 +53,28 @@ default ROM_SIZE = 512*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 11 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 11 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ## IDE Support default CONFIG_IDE = 1 @@ -83,36 +83,36 @@ default CONFIG_IDE = 1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -122,21 +122,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -148,13 +148,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 default CONFIG_UDELAY_TSC=1 diff --git a/src/mainboard/asus/mew-vm/auto.c b/src/mainboard/asus/mew-vm/auto.c index 721f6116b1..f53083f2a5 100644 --- a/src/mainboard/asus/mew-vm/auto.c +++ b/src/mainboard/asus/mew-vm/auto.c @@ -58,7 +58,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb index cb886bf914..a0486cd209 100644 --- a/src/mainboard/asus/p2b-d/Config.lb +++ b/src/mainboard/asus/p2b-d/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb index 946cc8a017..2409c14956 100644 --- a/src/mainboard/asus/p2b-d/Options.lb +++ b/src/mainboard/asus/p2b-d/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 0 diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c index f25e34e578..747ba77b35 100644 --- a/src/mainboard/asus/p2b-d/auto.c +++ b/src/mainboard/asus/p2b-d/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c index e8c6ff197d..05a465cc94 100644 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b-d/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb index 8d83be9ef1..2b6599458a 100644 --- a/src/mainboard/asus/p2b-ds/Config.lb +++ b/src/mainboard/asus/p2b-ds/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb index f907eac3d8..c069939fc5 100644 --- a/src/mainboard/asus/p2b-ds/Options.lb +++ b/src/mainboard/asus/p2b-ds/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c index 95cfa64765..aaa7ae94e6 100644 --- a/src/mainboard/asus/p2b-ds/auto.c +++ b/src/mainboard/asus/p2b-ds/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index bc3a64741c..29b6f54885 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb index 5bef9da403..f6995beedf 100644 --- a/src/mainboard/asus/p2b-f/Config.lb +++ b/src/mainboard/asus/p2b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p2b-f/Options.lb +++ b/src/mainboard/asus/p2b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c index 0c81b7f0d0..191c9ffd4c 100644 --- a/src/mainboard/asus/p2b-f/auto.c +++ b/src/mainboard/asus/p2b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index bbdf7bd9ae..f33c8cab55 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb index 2b54440f30..ef04497653 100644 --- a/src/mainboard/asus/p2b/Config.lb +++ b/src/mainboard/asus/p2b/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb index e6bd850cbd..db9fcecb29 100644 --- a/src/mainboard/asus/p2b/Options.lb +++ b/src/mainboard/asus/p2b/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c index 2e60b1c526..1b5891e519 100644 --- a/src/mainboard/asus/p2b/auto.c +++ b/src/mainboard/asus/p2b/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index f957dc878d..e0daa56076 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb index 1b752437c4..67b4b39627 100644 --- a/src/mainboard/asus/p3b-f/Config.lb +++ b/src/mainboard/asus/p3b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p3b-f/Options.lb +++ b/src/mainboard/asus/p3b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c index b4880d556b..e300bf6794 100644 --- a/src/mainboard/asus/p3b-f/auto.c +++ b/src/mainboard/asus/p3b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 47ef7f2f70..2cc0565431 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb index 68978705ce..54aae5352e 100644 --- a/src/mainboard/axus/tc320/Config.lb +++ b/src/mainboard/axus/tc320/Config.lb @@ -18,36 +18,36 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -57,7 +57,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb index 0003852a59..3fc2088f03 100644 --- a/src/mainboard/axus/tc320/Options.lb +++ b/src/mainboard/axus/tc320/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "AXUS" -default MAINBOARD_PART_NUMBER = "TC320" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "AXUS" +default CONFIG_MAINBOARD_PART_NUMBER = "TC320" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/axus/tc320/auto.c b/src/mainboard/axus/tc320/auto.c index 444771958c..ad80e5ce70 100644 --- a/src/mainboard/axus/tc320/auto.c +++ b/src/mainboard/axus/tc320/auto.c @@ -37,7 +37,7 @@ static void main(unsigned long bist) { - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c index 8a8ada270a..38e1567942 100644 --- a/src/mainboard/axus/tc320/irq_tables.c +++ b/src/mainboard/axus/tc320/irq_tables.c @@ -66,7 +66,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* PIRQ signature */ .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 + 16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ .rtr_bus = 0x00, /* Interrupt router bus */ .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb index 2c62f2ef25..fce9062c01 100644 --- a/src/mainboard/azza/pt-6ibd/Config.lb +++ b/src/mainboard/azza/pt-6ibd/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/azza/pt-6ibd/Options.lb +++ b/src/mainboard/azza/pt-6ibd/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/azza/pt-6ibd/auto.c b/src/mainboard/azza/pt-6ibd/auto.c index 8f64154f9e..24359a1038 100644 --- a/src/mainboard/azza/pt-6ibd/auto.c +++ b/src/mainboard/azza/pt-6ibd/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/azza/pt-6ibd/irq_tables.c b/src/mainboard/azza/pt-6ibd/irq_tables.c index 5de013f197..f7ec127c0c 100644 --- a/src/mainboard/azza/pt-6ibd/irq_tables.c +++ b/src/mainboard/azza/pt-6ibd/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb index bbd74bb076..7ea700dcfa 100644 --- a/src/mainboard/bcom/winnet100/Config.lb +++ b/src/mainboard/bcom/winnet100/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb index 384d78ce0a..2d18d267dd 100644 --- a/src/mainboard/bcom/winnet100/Options.lb +++ b/src/mainboard/bcom/winnet100/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "BCOM" -default MAINBOARD_PART_NUMBER = "WinNET100" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "BCOM" +default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/bcom/winnet100/auto.c b/src/mainboard/bcom/winnet100/auto.c index 9880011670..51d847b976 100644 --- a/src/mainboard/bcom/winnet100/auto.c +++ b/src/mainboard/bcom/winnet100/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/bcom/winnet100/irq_tables.c b/src/mainboard/bcom/winnet100/irq_tables.c index 9f711d86d2..b0cbc92fe6 100644 --- a/src/mainboard/bcom/winnet100/irq_tables.c +++ b/src/mainboard/bcom/winnet100/irq_tables.c @@ -64,7 +64,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* PIRQ signature */ .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 +16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .size = 32 +16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ .rtr_bus = 0x00, /* Interrupt router bus */ .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb index 29cf36d932..850f8e1326 100644 --- a/src/mainboard/bcom/winnetp680/Config.lb +++ b/src/mainboard/bcom/winnetp680/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/bcom/winnetp680/Options.lb b/src/mainboard/bcom/winnetp680/Options.lb index 446cf228b5..a6e1cfae00 100644 --- a/src/mainboard/bcom/winnetp680/Options.lb +++ b/src/mainboard/bcom/winnetp680/Options.lb @@ -19,46 +19,46 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -68,33 +68,33 @@ uses CONFIG_MAX_PCI_BUSES uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/bcom/winnetp680/auto.c b/src/mainboard/bcom/winnetp680/auto.c index af78949118..01135f8b5c 100644 --- a/src/mainboard/bcom/winnetp680/auto.c +++ b/src/mainboard/bcom/winnetp680/auto.c @@ -99,7 +99,7 @@ static void main(unsigned long bist) w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/bcom/winnetp680/irq_tables.c b/src/mainboard/bcom/winnetp680/irq_tables.c index fef553e219..9037e344a2 100644 --- a/src/mainboard/bcom/winnetp680/irq_tables.c +++ b/src/mainboard/bcom/winnetp680/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb index 75c6ae5588..6f3175f217 100644 --- a/src/mainboard/biostar/m6tba/Config.lb +++ b/src/mainboard/biostar/m6tba/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/biostar/m6tba/Options.lb +++ b/src/mainboard/biostar/m6tba/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/biostar/m6tba/auto.c b/src/mainboard/biostar/m6tba/auto.c index f68db56156..5a6244900e 100644 --- a/src/mainboard/biostar/m6tba/auto.c +++ b/src/mainboard/biostar/m6tba/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/biostar/m6tba/irq_tables.c b/src/mainboard/biostar/m6tba/irq_tables.c index ea01effd2b..b491510019 100644 --- a/src/mainboard/biostar/m6tba/irq_tables.c +++ b/src/mainboard/biostar/m6tba/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb index 9aae740958..e82bc9cf30 100644 --- a/src/mainboard/broadcom/blast/Config.lb +++ b/src/mainboard/broadcom/blast/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,8 +12,8 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end @@ -23,15 +23,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -55,7 +55,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end @@ -209,14 +209,14 @@ chip northbridge/amd/amdk8/root_complex device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if HT_CHAIN_END_UNITID_BASE=0, it is 5, if HT_CHAIN_END_UNITID_BASE=1, it is 4 + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 register "rom_address" = "0xfff80000" end end - #when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,) + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) # chip drivers/pci/onboard # device pci 0.0 on end # fake, will be disabled # end diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb index 752007572c..4f8e7b06d8 100644 --- a/src/mainboard/broadcom/blast/Options.lb +++ b/src/mainboard/broadcom/blast/Options.lb @@ -1,123 +1,123 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -129,27 +129,27 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 #default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset -default HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x6 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -160,38 +160,38 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="blast" -default MAINBOARD_VENDOR="Broadcom" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="blast" +default CONFIG_MAINBOARD_VENDOR="Broadcom" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -205,8 +205,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -223,21 +223,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -249,17 +249,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c index 2a06555b76..f8eb8c8535 100644 --- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -110,7 +110,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -161,14 +161,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x25); ; } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -197,7 +197,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // post_code(0x33); uart_init(); diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index b11d940399..b86292b0db 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -83,7 +83,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0)); if(dev) { bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -99,7 +99,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1,0)); if(dev) { bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb index 8f440c4cab..8dcd0402cc 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c index 032dd6f0d4..424f6f698b 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: Should be PC97307! */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c index f8bf246d21..7c59595422 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x14 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb index 0e305e3bf9..90f0181888 100644 --- a/src/mainboard/dell/s1850/Config.lb +++ b/src/mainboard/dell/s1850/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/dell/s1850/Options.lb +++ b/src/mainboard/dell/s1850/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c index 627acb4ca5..a80ba60b5b 100644 --- a/src/mainboard/dell/s1850/auto.c +++ b/src/mainboard/dell/s1850/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb index 91e0b844ec..c6401dd299 100644 --- a/src/mainboard/digitallogic/adl855pc/Config.lb +++ b/src/mainboard/digitallogic/adl855pc/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,29 +13,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -49,7 +49,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -71,7 +71,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb index 24cb38cbd8..aed66c00e7 100644 --- a/src/mainboard/digitallogic/adl855pc/Options.lb +++ b/src/mainboard/digitallogic/adl855pc/Options.lb @@ -1,47 +1,47 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_UDELAY_IO -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 1024*1024 +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 1024*1024 ### ### Build options @@ -50,17 +50,17 @@ default ROM_SIZE = 1024*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## use io based udelay function @@ -70,48 +70,48 @@ default CONFIG_UDELAY_IO=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/auto.c index 04cf2a359f..61351ba5a9 100644 --- a/src/mainboard/digitallogic/adl855pc/auto.c +++ b/src/mainboard/digitallogic/adl855pc/auto.c @@ -78,7 +78,7 @@ static void main(unsigned long bist) #endif } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb index 8f649b7964..0c28cc907d 100644 --- a/src/mainboard/digitallogic/msm586seg/Config.lb +++ b/src/mainboard/digitallogic/msm586seg/Config.lb @@ -1,8 +1,8 @@ -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 0x10000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = 0x10000 -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 32 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 32 * 1024 include /config/nofailovercalculation.lb ## @@ -16,29 +16,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -52,7 +52,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -74,7 +74,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb index fc9a2be178..68914e963c 100644 --- a/src/mainboard/digitallogic/msm586seg/Options.lb +++ b/src/mainboard/digitallogic/msm586seg/Options.lb @@ -1,47 +1,47 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_USE_INIT -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL # VGA support uses CONFIG_CONSOLE_VGA @@ -51,10 +51,10 @@ uses CONFIG_PCI_ROM_RUN default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -63,63 +63,63 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index b64a927bd7..b8f2150e78 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -137,7 +137,7 @@ static void enable_dev(struct device *dev) { /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x2000000 + 0x40000; - rom_end = rom_start + PAYLOAD_SIZE - 1; + rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; } diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb index 5256f09f54..f07835d7ce 100644 --- a/src/mainboard/digitallogic/msm800sev/Config.lb +++ b/src/mainboard/digitallogic/msm800sev/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,14 +14,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb index 3eede13583..c18a7c7ff0 100644 --- a/src/mainboard/digitallogic/msm800sev/Options.lb +++ b/src/mainboard/digitallogic/msm800sev/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c index e9dc8aec76..454031e782 100644 --- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c +++ b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c @@ -81,7 +81,7 @@ void cache_as_ram_main(void) * for cs5536 */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb index d8895573b2..d1f02be8c5 100644 --- a/src/mainboard/eaglelion/5bcm/Config.lb +++ b/src/mainboard/eaglelion/5bcm/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb index 6c4034120f..ad8fd92677 100644 --- a/src/mainboard/eaglelion/5bcm/Options.lb +++ b/src/mainboard/eaglelion/5bcm/Options.lb @@ -1,52 +1,52 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -55,17 +55,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -75,50 +75,50 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -128,21 +128,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -154,13 +154,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/eaglelion/5bcm/auto.c b/src/mainboard/eaglelion/5bcm/auto.c index b49039773a..096cebe2f7 100644 --- a/src/mainboard/eaglelion/5bcm/auto.c +++ b/src/mainboard/eaglelion/5bcm/auto.c @@ -23,7 +23,7 @@ static void main(unsigned long bist) { - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb index 551eebca67..4f7f808cec 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Config.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb @@ -23,5 +23,5 @@ end ## Build the objects we have code for in this directory. ## -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -msoft-float diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb index 7aabc4f252..c61cc6d2c4 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -2,25 +2,25 @@ ## Config file for the Embedded Planet EP405PC Computing Engine ## -uses PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGADDR uses CONFIG_CBFS uses CONFIG_ARCH_X86 -uses PCIC0_CFGDATA -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses TTYS0_BASE -uses _IO_BASE - -uses CPU_OPT -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_TTYS0_BASE +uses CONFIG_IO_BASE + +uses CONFIG_CPU_OPT +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_CHIP_CONFIGURE -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD TTYS0_DIV -uses NO_POST +uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV +uses CONFIG_NO_POST uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 @@ -28,54 +28,54 @@ uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses AUTOBOOT_CMDLINE +uses CONFIG_AUTOBOOT_CMDLINE uses CONFIG_SYS_CLK_FREQ -uses IDE_BOOT_DRIVE -#uses IDE_SWAB -uses IDE_OFFSET -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -#uses _RAMSTART -uses EMBEDDED_RAM_SIZE -uses STACK_SIZE HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IDE_BOOT_DRIVE +#uses CONFIG_IDE_SWAB +uses CONFIG_IDE_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +#uses CONFIG_RAMSTART +uses CONFIG_EMBEDDED_RAM_SIZE +uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set PCI configuration register addresses ## -default PCIC0_CFGADDR=0xeec00000 -default PCIC0_CFGDATA=0xeec00004 +default CONFIG_PCIC0_CFGADDR=0xeec00000 +default CONFIG_PCIC0_CFGDATA=0xeec00004 ## ## Set PCI/ISA I/O and memory base address ## -default ISA_IO_BASE=0xe8000000 -default ISA_MEM_BASE=0x80000000 -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xe8000000 +default CONFIG_ISA_MEM_BASE=0x80000000 +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## HACK ALERT: the UART0 registers are not in the PCI I/O address space ## but both IDE and UART use the same routines for I/O (inb/outb). To get ## around this we set TTYSO_BASE to the difference between the two. ## -default TTYS0_BASE=0xef600300-ISA_IO_BASE +default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE ## Enable PPC405 instructions -default CPU_OPT="-mcpu=405" -#default CPU_OPT="" +default CONFIG_CPU_OPT="-mcpu=405" +#default CONFIG_CPU_OPT="" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -88,14 +88,14 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 # Divisor of 69 == 9600 baud due to weird clocking -default TTYS0_DIV=69 -default TTYS0_BAUD=9600 +default CONFIG_TTYS0_DIV=69 +default CONFIG_TTYS0_BAUD=9600 ## Boot linux from IDE default CONFIG_IDE=1 @@ -103,25 +103,25 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hda1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz" -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## Board has fixed size RAM -default EMBEDDED_RAM_SIZE=64*1024*1024 +default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Use a 64K stack ## -default STACK_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 ## ## Use a 64K heap ## -default HEAP_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 ## ## System clock @@ -129,19 +129,19 @@ default HEAP_SIZE=0x10000 default CONFIG_SYS_CLK_FREQ=33 ## -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Reset vector address -default _RESET=0xfffffffc +default CONFIG_RESET=0xfffffffc ## Exception vectors -default _EXCEPTION_VECTORS=_ROMBASE+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100 ## coreboot ROM start address -default _ROMSTART=0xfff03000 +default CONFIG_ROMSTART=0xfff03000 ## coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ### End Options.lb # diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb index cabcb2deeb..78e5936ffc 100644 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ b/src/mainboard/emulation/qemu-x86/Config.lb @@ -1,34 +1,34 @@ -## we don't use USE_DCACHE_RAM by default -default USE_DCACHE_RAM=0 +## we don't use CONFIG_USE_DCACHE_RAM by default +default CONFIG_USE_DCACHE_RAM=0 ## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_IMAGE_SIZE -default ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2. +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_SIZE=32*1024 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default CONFIG_XIP_ROM_SIZE=32*1024 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture @@ -41,15 +41,15 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -## ALL dependencies for USE_DCACHE_RAM go here. +## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. ## That way, later, we can simply yank them if we wish. -## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case. +## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. ## we do not use failover yet in this case. This is a work in progress. -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM ## ## mainboardinit arch/i386/init/entry.S @@ -63,22 +63,22 @@ else ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -112,7 +112,7 @@ else ldscript /arch/i386/lib/id.lds ## -## end of USE_DCACHE_RAM bits. +## end of CONFIG_USE_DCACHE_RAM bits. ## end diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb index fdb69ffc47..191c6c6a41 100644 --- a/src/mainboard/emulation/qemu-x86/Options.lb +++ b/src/mainboard/emulation/qemu-x86/Options.lb @@ -1,63 +1,63 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_HIGH_TABLES -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_PCI_ROM_RUN uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_CONSOLE_SERIAL8250 -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CBFS default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_CBFS=1 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -66,30 +66,30 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Option ROM init @@ -101,40 +101,40 @@ default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = ROM_IMAGE_SIZE +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## known-good settings for qemu -default DCACHE_RAM_BASE=0x8f000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0x8f000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb index 339c6b1a94..acc09b495e 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Config.lb +++ b/src/mainboard/gigabyte/ga-6bxc/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Options.lb +++ b/src/mainboard/gigabyte/ga-6bxc/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/gigabyte/ga-6bxc/auto.c b/src/mainboard/gigabyte/ga-6bxc/auto.c index e67431afc5..9947d20e97 100644 --- a/src/mainboard/gigabyte/ga-6bxc/auto.c +++ b/src/mainboard/gigabyte/ga-6bxc/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c index bcc1fcd21b..a56c62d3f8 100644 --- a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c +++ b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb index c395fb738f..104ace034d 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -21,8 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -35,30 +35,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -68,13 +68,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -93,8 +93,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -102,7 +102,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -120,13 +120,13 @@ ldscript /southbridge/sis/sis966/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/sis/sis966/romstrap.inc ldscript /southbridge/sis/sis966/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/sis/sis966/romstrap.inc ldscript /southbridge/sis/sis966/romstrap.lds end @@ -142,12 +142,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb index a57533bfe2..b84498b658 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -21,90 +21,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,9 +112,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -123,21 +123,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -145,40 +145,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -189,25 +189,25 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -216,16 +216,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=0 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ga_2761gxdk" -default MAINBOARD_VENDOR="GIGABYTE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 +default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk" +default CONFIG_MAINBOARD_VENDOR="GIGABYTE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c index 35f2e63896..6fb051e7c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c @@ -88,8 +88,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c index f5c77ffee5..e44f4335b4 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -41,7 +41,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -58,7 +58,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -82,7 +82,7 @@ #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -154,7 +154,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -221,7 +221,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -234,21 +234,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -261,7 +261,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -272,7 +272,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -292,7 +292,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index 64864cd3a0..3f69d6f0e5 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,17 +140,17 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end -if HAVE_FANCTL +if CONFIG_HAVE_FANCTL object fanctl.o end @@ -166,11 +166,11 @@ end ## ## ACPI Support ## -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(PWD)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb index bcaba18376..7f96271069 100644 --- a/src/mainboard/gigabyte/m57sli/Options.lb +++ b/src/mainboard/gigabyte/m57sli/Options.lb @@ -19,92 +19,92 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,33 +112,33 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses HAVE_FANCTL +uses CONFIG_HAVE_FANCTL ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -146,48 +146,48 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Set-up automatic fan control ## -default HAVE_FANCTL=1 +default CONFIG_HAVE_FANCTL=1 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## HIGH tables support -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -198,25 +198,25 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -225,16 +225,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -242,15 +242,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -260,37 +260,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="m57sli" -default MAINBOARD_VENDOR="GIGABYTE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="m57sli" +default CONFIG_MAINBOARD_VENDOR="GIGABYTE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -306,8 +306,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -323,21 +323,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -349,17 +349,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/gigabyte/m57sli/apc_auto.c b/src/mainboard/gigabyte/m57sli/apc_auto.c index 7c09ae4818..d0730b935a 100644 --- a/src/mainboard/gigabyte/m57sli/apc_auto.c +++ b/src/mainboard/gigabyte/m57sli/apc_auto.c @@ -86,8 +86,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index 5462c31891..ab604c02b1 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -152,7 +152,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -219,7 +219,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -232,21 +232,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -259,7 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -281,10 +281,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(GPIO_DEV, 0x64, 0x08); pnp_write_config(GPIO_DEV, 0x65, 0x20); /* We can get away with not resetting the logical device because - * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that. + * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that. */ } - it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -304,7 +304,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/hp/dl145_g3/Config.lb b/src/mainboard/hp/dl145_g3/Config.lb index f493dda3c6..12ea977bab 100644 --- a/src/mainboard/hp/dl145_g3/Config.lb +++ b/src/mainboard/hp/dl145_g3/Config.lb @@ -25,8 +25,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -40,18 +40,18 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -60,7 +60,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -78,7 +78,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -102,7 +102,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb index a66c599901..283e37a3be 100644 --- a/src/mainboard/hp/dl145_g3/Options.lb +++ b/src/mainboard/hp/dl145_g3/Options.lb @@ -24,84 +24,84 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT uses CONFIG_CBFS -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -114,14 +114,14 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=ROM_IMAGE_SIZE +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -129,37 +129,37 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -170,41 +170,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=0 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_UNITID_BASE=0x06 #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x01 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -212,10 +212,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x04000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x04000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -226,37 +226,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="DL145 G3" -default MAINBOARD_VENDOR="HP" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3" +default CONFIG_MAINBOARD_VENDOR="HP" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -270,8 +270,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -289,21 +289,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -315,17 +315,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## CBFS diff --git a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c index c2269698e8..c3aeca615e 100644 --- a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c +++ b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c @@ -44,7 +44,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -62,7 +62,7 @@ #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -84,7 +84,7 @@ #include "superio/nsc/pc87417/pc87417_early_serial.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "northbridge/amd/amdk8/early_ht.c" @@ -238,7 +238,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -253,21 +253,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -283,7 +283,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; @@ -293,7 +293,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - pilot_enable_serial(SERIAL_DEV, TTYS0_BASE); + pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); //setup_mp_resource_map(); @@ -310,7 +310,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index d5732d0738..65a0eb9796 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -108,7 +108,7 @@ void get_bus_conf(void) printk_debug("now found %s...\n",dev_path(dev)); if(dev) { m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa 1=%d\n",m->bus_isa); @@ -124,7 +124,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); if(dev) { m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa 2=%d\n",m->bus_isa); diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb index 86fc7d21f5..0c7cd33d89 100644 --- a/src/mainboard/ibm/e325/Config.lb +++ b/src/mainboard/ibm/e325/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb index 98f61b1e0f..475863c2ca 100644 --- a/src/mainboard/ibm/e325/Options.lb +++ b/src/mainboard/ibm/e325/Options.lb @@ -1,54 +1,54 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -58,48 +58,48 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -117,45 +117,45 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="E325" -default MAINBOARD_VENDOR="IBM" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="E325" +default CONFIG_MAINBOARD_VENDOR="IBM" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -169,8 +169,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_USE_PRINTK_IN_CAR=1 @@ -182,21 +182,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -208,17 +208,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/ibm/e325/cache_as_ram_auto.c b/src/mainboard/ibm/e325/cache_as_ram_auto.c index 98a5a99db9..a6d32b64a0 100644 --- a/src/mainboard/ibm/e325/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e325/cache_as_ram_auto.c @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -145,7 +145,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -183,7 +183,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c index f340a2d31e..cfc28dd0a3 100644 --- a/src/mainboard/ibm/e325/irq_tables.c +++ b/src/mainboard/ibm/e325/irq_tables.c @@ -1,7 +1,7 @@ #include <arch/pirq_routing.h> #include <device/pci.h> -#define IRQ_SLOT_COUNT 12 +#define CONFIG_IRQ_SLOT_COUNT 12 #define IRQ_ROUTER_BUS 0 #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) #define IRQ_ROUTER_VENDOR 0x1022 @@ -19,7 +19,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb index 75a6be6c94..92a0c52145 100644 --- a/src/mainboard/ibm/e326/Config.lb +++ b/src/mainboard/ibm/e326/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/ibm/e326/Options.lb b/src/mainboard/ibm/e326/Options.lb index 9a101d1950..8406ecf84b 100644 --- a/src/mainboard/ibm/e326/Options.lb +++ b/src/mainboard/ibm/e326/Options.lb @@ -1,56 +1,56 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -60,48 +60,48 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -123,45 +123,45 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="E326" -default MAINBOARD_VENDOR="IBM" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="E326" +default CONFIG_MAINBOARD_VENDOR="IBM" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -175,8 +175,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_USE_PRINTK_IN_CAR=1 @@ -188,21 +188,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -214,17 +214,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/ibm/e326/cache_as_ram_auto.c b/src/mainboard/ibm/e326/cache_as_ram_auto.c index 872351323d..b036c62f11 100644 --- a/src/mainboard/ibm/e326/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e326/cache_as_ram_auto.c @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -145,7 +145,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -183,7 +183,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c index f340a2d31e..cfc28dd0a3 100644 --- a/src/mainboard/ibm/e326/irq_tables.c +++ b/src/mainboard/ibm/e326/irq_tables.c @@ -1,7 +1,7 @@ #include <arch/pirq_routing.h> #include <device/pci.h> -#define IRQ_SLOT_COUNT 12 +#define CONFIG_IRQ_SLOT_COUNT 12 #define IRQ_ROUTER_BUS 0 #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) #define IRQ_ROUTER_VENDOR 0x1022 @@ -19,7 +19,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb index 345f981510..fcc70fd703 100644 --- a/src/mainboard/iei/juki-511p/Config.lb +++ b/src/mainboard/iei/juki-511p/Config.lb @@ -2,31 +2,31 @@ ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_SIZE -default ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_SIZE +default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2. +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default CONFIG_XIP_ROM_SIZE=65536 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture @@ -40,29 +40,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb index 2e91257805..acedd0f765 100644 --- a/src/mainboard/iei/juki-511p/Options.lb +++ b/src/mainboard/iei/juki-511p/Options.lb @@ -1,53 +1,53 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_UDELAY_IO -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -56,57 +56,57 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 default CONFIG_UDELAY_IO=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=2 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=0 +default CONFIG_IRQ_SLOT_COUNT=2 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 @@ -116,32 +116,32 @@ default CONFIG_ROM_PAYLOAD = 1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/iei/juki-511p/auto.c b/src/mainboard/iei/juki-511p/auto.c index d24dee98d7..8486e82d55 100644 --- a/src/mainboard/iei/juki-511p/auto.c +++ b/src/mainboard/iei/juki-511p/auto.c @@ -40,7 +40,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb index 50b4029a1d..c567647a99 100644 --- a/src/mainboard/iei/nova4899r/Config.lb +++ b/src/mainboard/iei/nova4899r/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb index 3b49675b70..5072017fd5 100644 --- a/src/mainboard/iei/nova4899r/Options.lb +++ b/src/mainboard/iei/nova4899r/Options.lb @@ -1,43 +1,43 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA @@ -46,10 +46,10 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -62,17 +62,17 @@ default CONFIG_PCI_ROM_RUN=1 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=0 +default CONFIG_HAVE_FALLBACK_BOOT=0 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -82,50 +82,50 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -135,21 +135,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -161,14 +161,14 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/iei/nova4899r/auto.c b/src/mainboard/iei/nova4899r/auto.c index 29fde67779..6b198f5337 100644 --- a/src/mainboard/iei/nova4899r/auto.c +++ b/src/mainboard/iei/nova4899r/auto.c @@ -39,7 +39,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iei/nova4899r/irq_tables.c b/src/mainboard/iei/nova4899r/irq_tables.c index 3591fff1ee..5886c20077 100644 --- a/src/mainboard/iei/nova4899r/irq_tables.c +++ b/src/mainboard/iei/nova4899r/irq_tables.c @@ -51,7 +51,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* u32 signature */ .version = PIRQ_VERSION, /* u16 version */ - .size = 32+16*IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */ + .size = 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */ .rtr_bus = 0x00, /* Where the interrupt router lies (bus) */ .rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ .exclusive_irqs = 0x4C20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb index 515ffd0246..e4ebbcb170 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb @@ -18,20 +18,20 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc - # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -39,7 +39,7 @@ mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -48,7 +48,7 @@ else end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb index a3034b0a45..8da41c1b04 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb @@ -18,93 +18,93 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_IO uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -default ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_CONSOLE_VGA = 0 default CONFIG_VIDEO_MB = 8 default CONFIG_PCI_ROM_RUN = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_IO = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 9 -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 32 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 9 +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 default CONFIG_USE_PRINTK_IN_CAR=1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c index 23a740aeb4..cccb4a7509 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c @@ -118,7 +118,7 @@ void cache_as_ram_main(void) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c index affbfc6790..6f6d38b865 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb index 4a2468ab03..01bcf82862 100644 --- a/src/mainboard/intel/jarrell/Config.lb +++ b/src/mainboard/intel/jarrell/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb index a0e1f9ecf6..efa594a9c2 100644 --- a/src/mainboard/intel/jarrell/Options.lb +++ b/src/mainboard/intel/jarrell/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY -uses MAX_REBOOT_CNT -uses USE_WATCHDOG_ON_BOOT +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY +uses CONFIG_MAX_REBOOT_CNT +uses CONFIG_USE_WATCHDOG_ON_BOOT ### @@ -63,23 +63,23 @@ uses USE_WATCHDOG_ON_BOOT ## ## Because we do the stutter start we need more attempts ## -default MAX_REBOOT_CNT=8 +default CONFIG_MAX_REBOOT_CNT=8 ## ## Use the watchdog to break out of a lockup condition ## -default USE_WATCHDOG_ON_BOOT=1 +default CONFIG_USE_WATCHDOG_ON_BOOT=1 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=2097152 +default CONFIG_ROM_SIZE=2097152 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -91,31 +91,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -133,40 +133,40 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="SE7520JR22D" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 +default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -181,8 +181,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -197,21 +197,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -223,17 +223,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c index 61b066adfd..9745f761f8 100644 --- a/src/mainboard/intel/jarrell/auto.c +++ b/src/mainboard/intel/jarrell/auto.c @@ -81,7 +81,7 @@ static void main(unsigned long bist) /* Setup the console */ pc87427_disable_dev(CONSOLE_SERIAL_DEV); pc87427_disable_dev(HIDDEN_SERIAL_DEV); - pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Enable Serial 2 lines instead of GPIO */ outb(0x2c, 0x2e); outb((inb(0x2f) & (~1<<1)), 0x2f); diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb index dd9ea4a5a6..0613d7d369 100644 --- a/src/mainboard/intel/mtarvon/Config.lb +++ b/src/mainboard/intel/mtarvon/Config.lb @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -32,29 +32,29 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -68,7 +68,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -90,7 +90,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb index 47e7ff05f8..f1e76b000e 100644 --- a/src/mainboard/intel/mtarvon/Options.lb +++ b/src/mainboard/intel/mtarvon/Options.lb @@ -17,56 +17,56 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -74,14 +74,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE = 2 * 1024 * 1024 +default CONFIG_ROM_SIZE = 2 * 1024 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -93,19 +93,19 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=1 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code for SMP support @@ -123,39 +123,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Mt. Arvon" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 +default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 ### ### Coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -186,21 +186,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -212,17 +212,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/intel/mtarvon/auto.c b/src/mainboard/intel/mtarvon/auto.c index dd4b76346c..59c4e2fbc1 100644 --- a/src/mainboard/intel/mtarvon/auto.c +++ b/src/mainboard/intel/mtarvon/auto.c @@ -86,7 +86,7 @@ static void main(unsigned long bist) } /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(0x4e, I3100_SP1, TTYS0_BASE); + i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c index 9a295999ef..ddf5d9f795 100644 --- a/src/mainboard/intel/mtarvon/irq_tables.c +++ b/src/mainboard/intel/mtarvon/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb index 0f57a779b5..4a80852317 100644 --- a/src/mainboard/intel/truxton/Config.lb +++ b/src/mainboard/intel/truxton/Config.lb @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -32,29 +32,29 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -68,7 +68,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -90,7 +90,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb index d4c777c4e2..48160b42f4 100644 --- a/src/mainboard/intel/truxton/Options.lb +++ b/src/mainboard/intel/truxton/Options.lb @@ -17,56 +17,56 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -74,14 +74,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE = 2 * 1024 * 1024 +default CONFIG_ROM_SIZE = 2 * 1024 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -93,19 +93,19 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=1 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code for SMP support @@ -123,39 +123,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Truxton" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 +default CONFIG_MAINBOARD_PART_NUMBER="Truxton" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 ### ### Coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -186,21 +186,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -212,17 +212,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb diff --git a/src/mainboard/intel/truxton/auto.c b/src/mainboard/intel/truxton/auto.c index 08c64dffe7..8176774fb3 100644 --- a/src/mainboard/intel/truxton/auto.c +++ b/src/mainboard/intel/truxton/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, TTYS0_BASE); + i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c index ce31ca3385..f7ed1c59e9 100644 --- a/src/mainboard/intel/truxton/irq_tables.c +++ b/src/mainboard/intel/truxton/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb index bf5c938dfe..2ac608f066 100644 --- a/src/mainboard/intel/xe7501devkit/Config.lb +++ b/src/mainboard/intel/xe7501devkit/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -9,9 +9,9 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES object acpi_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o end object reset.o # Include the VGA option ROM, but only if we're compiled to use it @@ -29,22 +29,22 @@ end ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -58,8 +58,8 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FALLBACK_BOOT - if USE_FALLBACK_IMAGE +if CONFIG_HAVE_FALLBACK_BOOT + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb index d3036df6a7..2420b6a1af 100644 --- a/src/mainboard/intel/xe7501devkit/Options.lb +++ b/src/mainboard/intel/xe7501devkit/Options.lb @@ -1,11 +1,11 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_PIRQ_TABLE -uses HAVE_FALLBACK_BOOT -uses HAVE_OPTION_TABLE -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_MAX_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_PHYSICAL_CPUS @@ -14,72 +14,72 @@ uses CONFIG_SMP uses CONFIG_ROM_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses DEBUG -#uses CPU_OPT +uses CONFIG_DEBUG +#uses CONFIG_CPU_OPT uses CONFIG_IDE ## The default definitions are used for these uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE ## These are defined in target Config.lb, don't add here -uses USE_FALLBACK_IMAGE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses FALLBACK_SIZE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_FALLBACK_SIZE uses COREBOOT_EXTRA_VERSION ## These are defined in mainboard Config.lb, don't add here -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=2097152 -default ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_SIZE=2097152 +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Build code for the fallback boot? ## -default HAVE_FALLBACK_BOOT=1 -default FALLBACK_SIZE=131072 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_FALLBACK_SIZE=131072 ## Delay timer options @@ -90,28 +90,28 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=12 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=12 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## Build code to export ACPI tables? -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table? ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## CMOS checksum definitions (units == bytes) ## These must match the checksum record in cmos.layout -default LB_CKS_RANGE_START=128 -default LB_CKS_RANGE_END=130 -default LB_CKS_LOC=131 +default CONFIG_LB_CKS_RANGE_START=128 +default CONFIG_LB_CKS_RANGE_END=130 +default CONFIG_LB_CKS_LOC=131 ## ## Build code for SMP support @@ -138,10 +138,10 @@ default CONFIG_IOAPIC=1 ## ## Motherboard identification ## -default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" -default MAINBOARD_VENDOR="Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 +default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" +default CONFIG_MAINBOARD_VENDOR="Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 ### ### coreboot layout values @@ -150,22 +150,22 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## CMOS settings not currently supported due to conflicts with factory BIOS ## -default USE_OPTION_TABLE = 0 +default CONFIG_USE_OPTION_TABLE = 0 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -179,8 +179,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -195,21 +195,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -221,23 +221,23 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## Things we may not have default CONFIG_IDE=1 -default DEBUG=1 -# default CPU_OPT="-g" +default CONFIG_DEBUG=1 +# default CONFIG_CPU_OPT="-g" ### End Options.lb # diff --git a/src/mainboard/intel/xe7501devkit/auto.c b/src/mainboard/intel/xe7501devkit/auto.c index b106595803..fc845a2ee9 100644 --- a/src/mainboard/intel/xe7501devkit/auto.c +++ b/src/mainboard/intel/xe7501devkit/auto.c @@ -66,7 +66,7 @@ static void main(unsigned long bist) // Get the serial port running and print a welcome banner - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb index faa294924f..54a66c7939 100644 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ b/src/mainboard/iwill/dk8_htx/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -15,25 +15,25 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -#if HAVE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES # object acpi_tables.o # object fadt.o -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object dsdt_bus0.o # else # object dsdt.o # end # object ssdt.o -# if ACPI_SSDTX_NUM -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_ACPI_SSDTX_NUM +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object ssdt2_bus0.o # else # object ssdt2.o @@ -41,43 +41,43 @@ end # end #end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -88,27 +88,27 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -118,13 +118,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -176,12 +176,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb index 305d8026bc..1f08f6a603 100644 --- a/src/mainboard/iwill/dk8_htx/Options.lb +++ b/src/mainboard/iwill/dk8_htx/Options.lb @@ -1,85 +1,85 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-8K -default FALLBACK_SIZE=0x3e000 +default CONFIG_FALLBACK_SIZE=0x3e000 #FAILOVER: 8K -default FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=3 +default CONFIG_ACPI_SSDTX_NUM=3 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -#default HW_MEM_HOLE_SIZEK=0x100000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -default HW_MEM_HOLE_SIZEK=0x80000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -207,18 +207,18 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## ## for rev F training on AP purpose ## #default CONFIG_AP_CODE_IN_CAR=1 -#default MEM_TRAIN_SEQ=1 -#default WAIT_BEFORE_CPUS_INIT=1 +#default CONFIG_MEM_TRAIN_SEQ=1 +#default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -228,37 +228,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="dk8_htx" -default MAINBOARD_VENDOR="IWILL" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx" +default CONFIG_MAINBOARD_VENDOR="IWILL" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -272,8 +272,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -289,21 +289,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -315,17 +315,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index c382e3e298..53822bd9d6 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -40,7 +40,7 @@ static void dump_mem(unsigned start, unsigned end) extern unsigned char AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern unsigned char AmlCode_ssdt2[]; extern unsigned char AmlCode_ssdt3[]; extern unsigned char AmlCode_ssdt4[]; @@ -266,7 +266,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table diff --git a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c index cb292bde7b..72c1b86b63 100644 --- a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index d49333c261..ae3b25dcb7 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -109,7 +109,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -132,7 +132,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb index bf1806b440..8f34a30aa3 100644 --- a/src/mainboard/iwill/dk8s2/Config.lb +++ b/src/mainboard/iwill/dk8s2/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,8 +13,8 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ATI Rage XL framebuffering graphics driver @@ -23,15 +23,15 @@ dir /drivers/ati/ragexl if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -41,7 +41,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -59,7 +59,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -83,7 +83,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb index 6c0fb018c3..e9a3bafc34 100644 --- a/src/mainboard/iwill/dk8s2/Options.lb +++ b/src/mainboard/iwill/dk8s2/Options.lb @@ -1,106 +1,106 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=524288 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=524288 ### ### Build options ### ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -118,46 +118,46 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="HDAMA" -default MAINBOARD_VENDOR="ARIMA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +default CONFIG_MAINBOARD_VENDOR="ARIMA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -171,8 +171,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -#default CC="$(CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" +#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +#default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -189,21 +189,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -215,17 +215,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c index 6716a55825..51617ab0ce 100644 --- a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb index 216cceb172..7e2dd6dbf5 100644 --- a/src/mainboard/iwill/dk8x/Config.lb +++ b/src/mainboard/iwill/dk8x/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb index a515945180..5b6cd23ed4 100644 --- a/src/mainboard/iwill/dk8x/Options.lb +++ b/src/mainboard/iwill/dk8x/Options.lb @@ -1,106 +1,106 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=524288 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=524288 ### ### Build options ### ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -118,45 +118,45 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -#default MAINBOARD_PART_NUMBER="HDAMA" -#default MAINBOARD_VENDOR="ARIMA" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +#default CONFIG_MAINBOARD_VENDOR="ARIMA" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -#default CC="$(CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" +#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +#default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -188,21 +188,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -214,17 +214,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c index 6716a55825..51617ab0ce 100644 --- a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c index 6322c3df21..1f35cbaef2 100644 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ b/src/mainboard/iwill/dk8x/irq_tables.c @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT * devices on the bus */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb index 832fe36251..bd33c3ffc1 100644 --- a/src/mainboard/jetway/j7f24/Config.lb +++ b/src/mainboard/jetway/j7f24/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/jetway/j7f24/Options.lb b/src/mainboard/jetway/j7f24/Options.lb index 1000212827..0bc79aa261 100644 --- a/src/mainboard/jetway/j7f24/Options.lb +++ b/src/mainboard/jetway/j7f24/Options.lb @@ -19,83 +19,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -#default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +#default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/jetway/j7f24/auto.c b/src/mainboard/jetway/j7f24/auto.c index 15764e932c..59697259cf 100644 --- a/src/mainboard/jetway/j7f24/auto.c +++ b/src/mainboard/jetway/j7f24/auto.c @@ -40,7 +40,7 @@ #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" -#if TTYS0_BASE == 0x2f8 +#if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) #else #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1) @@ -101,7 +101,7 @@ static void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - f71805f_enable_serial(SERIAL_DEV, TTYS0_BASE); + f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/jetway/j7f24/irq_tables.c b/src/mainboard/jetway/j7f24/irq_tables.c index fef553e219..9037e344a2 100644 --- a/src/mainboard/jetway/j7f24/irq_tables.c +++ b/src/mainboard/jetway/j7f24/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index 303b4e5840..b768bf326c 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -26,10 +26,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -44,16 +44,16 @@ arch i386 end driver mainboard.o driver rtl8168.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_SMI_HANDLER smmobject mainboard_smi.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv $(CURDIR)/dsdt.hex dsdt.c" end object ./dsdt.o @@ -64,15 +64,15 @@ object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -93,7 +93,7 @@ end ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,7 +118,7 @@ mainboardinit cpu/intel/model_6ex/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb index f4ab0dfd77..07c139f98a 100644 --- a/src/mainboard/kontron/986lcd-m/Options.lb +++ b/src/mainboard/kontron/986lcd-m/Options.lb @@ -20,17 +20,17 @@ ## # Tables -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_MAINBOARD_RESOURCES # SMP uses CONFIG_SMP uses CONFIG_LOGICAL_CPUS @@ -39,71 +39,71 @@ uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC # Image Size -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET # Payload uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE # Build Internals -uses _RAMBASE -uses _ROMBASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses XIP_ROM_BASE -uses XIP_ROM_SIZE -uses HAVE_HARD_RESET -uses HAVE_SMI_HANDLER +uses CONFIG_XIP_ROM_BASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_SMI_HANDLER uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses MMCONF_SUPPORT -uses MMCONF_BASE_ADDRESS +uses CONFIG_MMCONF_SUPPORT +uses CONFIG_MMCONF_BASE_ADDRESS uses CONFIG_GFXUMA uses CONFIG_CBFS # -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID # Timers uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 # Console uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses DEBUG +uses CONFIG_DEBUG # Toolchain uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY # Tweaks uses CONFIG_GDB_STUB -uses MAX_REBOOT_CNT -uses USE_WATCHDOG_ON_BOOT +uses CONFIG_MAX_REBOOT_CNT +uses CONFIG_USE_WATCHDOG_ON_BOOT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ### ### Build options @@ -111,23 +111,23 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL ## ## -default MAX_REBOOT_CNT=3 +default CONFIG_MAX_REBOOT_CNT=3 ## ## Use the watchdog to break out of a lockup condition ## -default USE_WATCHDOG_ON_BOOT=0 +default CONFIG_USE_WATCHDOG_ON_BOOT=0 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 +default CONFIG_ROM_SIZE=1024*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -139,20 +139,20 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=1 +default CONFIG_HAVE_SMI_HANDLER=1 ## ## Leave a hole for mmapped PCIe config space ## default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default MMCONF_SUPPORT=1 -default MMCONF_BASE_ADDRESS=0xf0000000 +default CONFIG_MMCONF_SUPPORT=1 +default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 ## ## UMA @@ -162,32 +162,32 @@ default CONFIG_GFXUMA=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=18 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=18 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -196,7 +196,7 @@ default CONFIG_CONSOLE_VGA=1 # for now: default CONFIG_VGA_ROM_RUN=1 default CONFIG_PCI_ROM_RUN=0 -default DEBUG=0 +default CONFIG_DEBUG=0 ## ## Build code for SMP support @@ -211,9 +211,9 @@ default CONFIG_AP_IN_SIPI_WAIT=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024) +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) default CONFIG_USE_PRINTK_IN_CAR=1 ## @@ -224,37 +224,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="986LCD-M" -default MAINBOARD_VENDOR= "KONTRON" +default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M" +default CONFIG_MAINBOARD_VENDOR= "KONTRON" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=ROM_IMAGE_SIZE +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -268,8 +268,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -284,21 +284,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -310,17 +310,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 2f9c1ec71f..c7c060f0a3 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start) printk_debug("ACPI: * DMI (Linux workaround)\n"); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); current += DMI_TABLE_SIZE; ALIGN_CURRENT; diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c index 06023e67af..781ef2ceba 100644 --- a/src/mainboard/kontron/986lcd-m/auto.c +++ b/src/mainboard/kontron/986lcd-m/auto.c @@ -296,7 +296,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801gx/cmos_failover.c" #endif @@ -331,7 +331,7 @@ void real_main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -351,7 +351,7 @@ void real_main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 #if defined(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); #endif diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb index 4dc35b58f1..daf513380f 100644 --- a/src/mainboard/lippert/frontrunner/Config.lb +++ b/src/mainboard/lippert/frontrunner/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb index 70c05bfa56..eff01c1087 100644 --- a/src/mainboard/lippert/frontrunner/Options.lb +++ b/src/mainboard/lippert/frontrunner/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -125,21 +125,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -151,13 +151,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/lippert/frontrunner/auto.c b/src/mainboard/lippert/frontrunner/auto.c index 781fe1d0d2..3bcad1f714 100644 --- a/src/mainboard/lippert/frontrunner/auto.c +++ b/src/mainboard/lippert/frontrunner/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) SystemPreInit(); msr_init(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb index 21c75d60fa..00b6713896 100644 --- a/src/mainboard/lippert/roadrunner-lx/Config.lb +++ b/src/mainboard/lippert/roadrunner-lx/Config.lb @@ -20,8 +20,8 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -36,14 +36,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end @@ -59,7 +59,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,7 +81,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb index d91f602534..530c43ea78 100644 --- a/src/mainboard/lippert/roadrunner-lx/Options.lb +++ b/src/mainboard/lippert/roadrunner-lx/Options.lb @@ -20,69 +20,69 @@ ## Based on Options.lb from AMD's DB800 mainboard. -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 -uses AUTOBOOT_DELAY -uses AUTOBOOT_CMDLINE -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_DELAY +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEBUG -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEBUG +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512 * 1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512 * 1024 ### ### Build options @@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## Delay timer options ## @@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default PIRQ_ROUTE = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE = 8 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 ## ## Use a small 16K heap ## -default HEAP_SIZE = 16 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" ## ## The Serial Console @@ -174,24 +174,24 @@ default HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD = 115200 -#default TTYS0_BAUD = 57600 -#default TTYS0_BAUD = 38400 -#default TTYS0_BAUD = 19200 -#default TTYS0_BAUD = 9600 -#default TTYS0_BAUD = 4800 -#default TTYS0_BAUD = 2400 -#default TTYS0_BAUD = 1200 +default CONFIG_TTYS0_BAUD = 115200 +#default CONFIG_TTYS0_BAUD = 57600 +#default CONFIG_TTYS0_BAUD = 38400 +#default CONFIG_TTYS0_BAUD = 19200 +#default CONFIG_TTYS0_BAUD = 9600 +#default CONFIG_TTYS0_BAUD = 4800 +#default CONFIG_TTYS0_BAUD = 2400 +#default CONFIG_TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS = 0x3 +default CONFIG_TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG = 1 +default CONFIG_DEBUG = 1 ## ### Select the coreboot loglevel @@ -203,13 +203,13 @@ default DEBUG = 1 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 # # CBFS diff --git a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c index 660a9de02f..6a07a05e44 100644 --- a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c +++ b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c @@ -103,7 +103,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x1E2C, // disable ATXPowerGood - will cause a reboot! 0x0423, // don't delay POWerOK1/2 0x9072, // watchdog triggers POWOK, counts seconds -#if !USE_WATCHDOG_ON_BOOT +#if !CONFIG_USE_WATCHDOG_ON_BOOT 0x0073, 0x0074, // disable watchdog by setting timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins @@ -149,7 +149,7 @@ void cache_as_ram_main(void) * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/irq_tables.c b/src/mainboard/lippert/roadrunner-lx/irq_tables.c index 4ee33d4245..0e7572da90 100644 --- a/src/mainboard/lippert/roadrunner-lx/irq_tables.c +++ b/src/mainboard/lippert/roadrunner-lx/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb index 0c2866a743..b74ce8b911 100644 --- a/src/mainboard/lippert/spacerunner-lx/Config.lb +++ b/src/mainboard/lippert/spacerunner-lx/Config.lb @@ -20,8 +20,8 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -35,14 +35,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -58,7 +58,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb index 5d8dd0981a..805148b7f2 100644 --- a/src/mainboard/lippert/spacerunner-lx/Options.lb +++ b/src/mainboard/lippert/spacerunner-lx/Options.lb @@ -20,69 +20,69 @@ ## Based on Options.lb from AMD's DB800 mainboard. -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 -uses AUTOBOOT_DELAY -uses AUTOBOOT_CMDLINE -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_DELAY +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEBUG -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEBUG +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## Delay timer options ## @@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default PIRQ_ROUTE = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE = 0x2000 +default CONFIG_STACK_SIZE = 0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE = 0x4000 +default CONFIG_HEAP_SIZE = 0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" ## ## The Serial Console @@ -174,24 +174,24 @@ default HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD = 115200 -#default TTYS0_BAUD = 57600 -#default TTYS0_BAUD = 38400 -#default TTYS0_BAUD = 19200 -#default TTYS0_BAUD = 9600 -#default TTYS0_BAUD = 4800 -#default TTYS0_BAUD = 2400 -#default TTYS0_BAUD = 1200 +default CONFIG_TTYS0_BAUD = 115200 +#default CONFIG_TTYS0_BAUD = 57600 +#default CONFIG_TTYS0_BAUD = 38400 +#default CONFIG_TTYS0_BAUD = 19200 +#default CONFIG_TTYS0_BAUD = 9600 +#default CONFIG_TTYS0_BAUD = 4800 +#default CONFIG_TTYS0_BAUD = 2400 +#default CONFIG_TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS = 0x3 +default CONFIG_TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG = 1 +default CONFIG_DEBUG = 1 ## ### Select the coreboot loglevel @@ -203,13 +203,13 @@ default DEBUG = 1 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 # # CBFS diff --git a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c index 08be2de149..af26262387 100644 --- a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c +++ b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c @@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if DEBUG +#if CONFIG_DEBUG if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err_hex8(address); @@ -165,7 +165,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x1E2C, // disable ATXPowerGood 0x0423, // don't delay POWerOK1/2 0x9072, // watchdog triggers POWOK, counts seconds -#if !USE_WATCHDOG_ON_BOOT +#if !CONFIG_USE_WATCHDOG_ON_BOOT 0x0073, 0x0074, // disable watchdog by setting timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins @@ -211,7 +211,7 @@ void cache_as_ram_main(void) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/lippert/spacerunner-lx/irq_tables.c b/src/mainboard/lippert/spacerunner-lx/irq_tables.c index df2b20a969..5350b57a4d 100644 --- a/src/mainboard/lippert/spacerunner-lx/irq_tables.c +++ b/src/mainboard/lippert/spacerunner-lx/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb index ee6abf85fd..5ed46bd3b7 100644 --- a/src/mainboard/motorola/sandpoint/Config.lb +++ b/src/mainboard/motorola/sandpoint/Config.lb @@ -15,7 +15,7 @@ initobject clock.o object clock.o ## -## Set our ARCH +## Set our CONFIG_ARCH ## arch ppc end @@ -26,5 +26,5 @@ arch ppc end dir nvram dir flash -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -g diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb index 239ebc4a08..7d50c39ce1 100644 --- a/src/mainboard/motorola/sandpoint/Options.lb +++ b/src/mainboard/motorola/sandpoint/Options.lb @@ -5,70 +5,70 @@ uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY uses CONFIG_SANDPOINT_VALIS uses CONFIG_SANDPOINT_GYRUS -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -81,12 +81,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -94,34 +94,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 default CONFIG_SANDPOINT_ALTIMUS=1 diff --git a/src/mainboard/motorola/sandpoint/init.c b/src/mainboard/motorola/sandpoint/init.c index 567a6aed70..42acd35164 100644 --- a/src/mainboard/motorola/sandpoint/init.c +++ b/src/mainboard/motorola/sandpoint/init.c @@ -38,8 +38,8 @@ void pnp_output(char address, char data) { - outb(address, PNP_CFGADDR); - outb(data, PNP_CFGDATA); + outb(address, CONFIG_PNP_CFGADDR); + outb(data, CONFIG_PNP_CFGDATA); } void @@ -55,10 +55,10 @@ board_init(void) */ pnp_output(0x07, 6); /* LD 6 = UART0 */ pnp_output(0x30, 0); /* Dectivate */ - pnp_output(0x60, TTYS0_BASE >> 8); /* IO Base */ - pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */ + pnp_output(0x60, CONFIG_TTYS0_BASE >> 8); /* IO Base */ + pnp_output(0x61, CONFIG_TTYS0_BASE & 0xFF); /* IO Base */ pnp_output(0x30, 1); /* Activate */ - uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, 115200/CONFIG_TTYS0_BAUD, CONFIG_TTYS0_LCS); } void diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb index 42b183f916..1a47974bf8 100644 --- a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb +++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb @@ -1,22 +1,22 @@ -uses ISA_IO_BASE +uses CONFIG_ISA_IO_BASE uses CONFIG_CBFS -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 @@ -24,47 +24,47 @@ uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" ## Use stage 1 initialization code default CONFIG_USE_INIT=1 @@ -76,12 +76,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -89,34 +89,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 ### End Options.lb # diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb index df78d8ee7a..608a458e47 100644 --- a/src/mainboard/msi/ms6119/Config.lb +++ b/src/mainboard/msi/ms6119/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6119/Options.lb b/src/mainboard/msi/ms6119/Options.lb index 31c70358f5..feb32318c7 100644 --- a/src/mainboard/msi/ms6119/Options.lb +++ b/src/mainboard/msi/ms6119/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/msi/ms6119/auto.c b/src/mainboard/msi/ms6119/auto.c index 8db62487d4..e5dd2055be 100644 --- a/src/mainboard/msi/ms6119/auto.c +++ b/src/mainboard/msi/ms6119/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6119/irq_tables.c b/src/mainboard/msi/ms6119/irq_tables.c index effdfae731..143a1104f5 100644 --- a/src/mainboard/msi/ms6119/irq_tables.c +++ b/src/mainboard/msi/ms6119/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x800, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb index ccae4ceeac..29601be4e4 100644 --- a/src/mainboard/msi/ms6147/Config.lb +++ b/src/mainboard/msi/ms6147/Config.lb @@ -18,34 +18,34 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -66,7 +66,7 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6147/Options.lb b/src/mainboard/msi/ms6147/Options.lb index 9e0f7225dd..79efc55c9f 100644 --- a/src/mainboard/msi/ms6147/Options.lb +++ b/src/mainboard/msi/ms6147/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/msi/ms6147/auto.c b/src/mainboard/msi/ms6147/auto.c index 6172743b40..a9a95a8689 100644 --- a/src/mainboard/msi/ms6147/auto.c +++ b/src/mainboard/msi/ms6147/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index fbea5319e1..b3cd1194a6 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb index 801a9b24d4..391ccf0f6f 100644 --- a/src/mainboard/msi/ms6178/Config.lb +++ b/src/mainboard/msi/ms6178/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb index 6e2277654b..67f52f37e5 100644 --- a/src/mainboard/msi/ms6178/Options.lb +++ b/src/mainboard/msi/ms6178/Options.lb @@ -18,84 +18,84 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default ROM_SIZE = 512 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_IMAGE_SIZE -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 1 -default HAVE_HIGH_TABLES = 1 +default CONFIG_HAVE_HIGH_TABLES = 1 end diff --git a/src/mainboard/msi/ms6178/auto.c b/src/mainboard/msi/ms6178/auto.c index a59074d17a..9d91b13018 100644 --- a/src/mainboard/msi/ms6178/auto.c +++ b/src/mainboard/msi/ms6178/auto.c @@ -49,7 +49,7 @@ static void main(unsigned long bist) outb(0x87, 0x2e); outb(0x87, 0x2e); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x87, 0xaa); uart_init(); diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c index 97cd2a6ec0..10159b3c52 100644 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ b/src/mainboard/msi/ms6178/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb index d316182ebd..5bd867b888 100644 --- a/src/mainboard/msi/ms7135/Config.lb +++ b/src/mainboard/msi/ms7135/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -39,23 +39,23 @@ driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -64,13 +64,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code. ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -86,8 +86,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (this is where coreboot is entered). ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -95,7 +95,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -113,13 +113,13 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -135,12 +135,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb index 36260c76e0..e5f8ead7e5 100644 --- a/src/mainboard/msi/ms7135/Options.lb +++ b/src/mainboard/msi/ms7135/Options.lb @@ -20,102 +20,102 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR uses CONFIG_USE_PRINTK_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## ---> 512 Kbytes -default ROM_SIZE=(512*1024) +default CONFIG_ROM_SIZE=(512*1024) ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=(252*1024) +default CONFIG_FALLBACK_SIZE=(252*1024) #FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) ### ### Build options @@ -124,37 +124,37 @@ default FAILOVER_SIZE=(4*1024) ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -166,19 +166,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -190,22 +190,22 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +#default CONFIG_DCACHE_RAM_BASE=0xcf000 +#default CONFIG_DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 +#default CONFIG_ENABLE_APIC_EXT_ID=0 +#default CONFIG_APIC_ID_OFFSET=0x10 +#default CONFIG_LIFT_BSP_APIC_ID=0 #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -218,39 +218,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 +default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = (64*1024) #65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -264,8 +264,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -282,21 +282,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -308,17 +308,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms7135/cache_as_ram_auto.c b/src/mainboard/msi/ms7135/cache_as_ram_auto.c index eaeeeb16e5..b8a22a97c5 100644 --- a/src/mainboard/msi/ms7135/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7135/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck804_early_setup(). */ #define CK804_NUM 1 @@ -101,10 +101,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -169,7 +169,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -178,27 +178,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -218,7 +218,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -270,4 +270,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb index fdea44ed0a..d17e0973f2 100644 --- a/src/mainboard/msi/ms7260/Config.lb +++ b/src/mainboard/msi/ms7260/Config.lb @@ -18,50 +18,50 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end driver mainboard.o object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables). -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -76,8 +76,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -98,13 +98,13 @@ mainboardinit southbridge/nvidia/mcp55/id.inc ldscript /southbridge/nvidia/mcp55/id.lds # ROMSTRAP table for MCP55. -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -112,12 +112,12 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb index b16ebcaf61..9c657d4d0b 100644 --- a/src/mainboard/msi/ms7260/Options.lb +++ b/src/mainboard/msi/ms7260/Options.lb @@ -18,137 +18,137 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER # ? -uses CROSS_COMPILE +uses CONFIG_HAVE_INIT_TIMER # ? +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_USBDEBUG_DIRECT -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_SERIAL_CPU_INIT +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = (256 * 1024) - (4 * 1024) -default FAILOVER_SIZE = 4 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = (256 * 1024) - (4 * 1024) +default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_FAILOVER_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 11 # TODO: Check if correct. -default HAVE_MP_TABLE = 1 # TODO: Check if correct. -default HAVE_OPTION_TABLE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. +default CONFIG_HAVE_MP_TABLE = 1 # TODO: Check if correct. +default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -# default SERIAL_CPU_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 1 +# default CONFIG_SERIAL_CPU_INIT = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 1 # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 # Memory hole size. 0 means disable, others will enable the hole. In that # case, if it is smaller than mmio_basek, it will use mmio_basek instead. -# default HW_MEM_HOLE_SIZEK = 0x200000 # 2GB -default HW_MEM_HOLE_SIZEK = 0x100000 # 1GB -# default HW_MEM_HOLE_SIZEK = 0x80000 # 512MB +# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000 # 2GB +default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # 1GB +# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 # 512MB # Make auto increase hole size to avoid hole_startk equal to basek so as # to make some kernel happy. -# default HW_MEM_HOLE_SIZE_AUTO_INC = 1 +# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1 # Opteron K8 1G HT support. -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one, 0 means only one HT device. -default HT_CHAIN_UNITID_BASE = 0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x6 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 # Make the SB HT chain on bus 0, default is not (0). -default SB_HT_CHAIN_ON_BUS0 = 2 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 # Only offset for SB chain? Default is yes (1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 # Allow capable device use that above 4GB. # default CONFIG_PCI_64BIT_PREF_MEM = 1 @@ -156,35 +156,35 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. default CONFIG_USBDEBUG_DIRECT = 0 -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 default CONFIG_AP_CODE_IN_CAR = 0 -default MEM_TRAIN_SEQ = 2 -default WAIT_BEFORE_CPUS_INIT = 0 +default CONFIG_MEM_TRAIN_SEQ = 2 +default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" -default MAINBOARD_VENDOR = "MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 -default ROM_IMAGE_SIZE = 65536 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x8000 -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) -default _RAMBASE = 0x00100000 +default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" +default CONFIG_MAINBOARD_VENDOR = "MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x8000 +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) +default CONFIG_RAMBASE = 0x00100000 default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c index 33217d1d8a..880952b267 100644 --- a/src/mainboard/msi/ms7260/apc_auto.c +++ b/src/mainboard/msi/ms7260/apc_auto.c @@ -61,10 +61,10 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - - DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) - - DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ struct node_core_id id; id = get_node_core_id_x(); diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c index c9e429d5ca..8089b577e0 100644 --- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c @@ -43,7 +43,7 @@ /* If we want to wait for core1 done before DQS training, set it to 0. */ #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -60,7 +60,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" @@ -82,7 +82,7 @@ #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -133,7 +133,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -194,7 +194,7 @@ normal_image: ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image": :"a" (bist), "b"(cpu_init_detectedx) ) @@ -207,21 +207,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -235,7 +235,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -246,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); #endif diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb index c40eb30ca3..99b86007af 100644 --- a/src/mainboard/msi/ms9185/Config.lb +++ b/src/mainboard/msi/ms9185/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -39,26 +39,26 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -68,7 +68,7 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -85,7 +85,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -109,7 +109,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end @@ -207,10 +207,10 @@ chip northbridge/amd/amdk8/root_complex device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if HT_CHAIN_END_UNITID_BASE=0, it is 4, if HT_CHAIN_END_UNITID_BASE=1, it is 3 + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 register "rom_address" = "0xfff80000" end #bx_a013+ start @@ -223,7 +223,7 @@ chip northbridge/amd/amdk8/root_complex #bx_a013+ end end - #when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,) + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) # chip drivers/pci/onboard # device pci 0.0 on end # fake, will be disabled # end diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb index 5c3073e2d2..f6567040d8 100644 --- a/src/mainboard/msi/ms9185/Options.lb +++ b/src/mainboard/msi/ms9185/Options.lb @@ -22,85 +22,85 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,16 +112,16 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -129,41 +129,41 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -#default HAVE_ACPI_TABLES=1 +#default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -#default ACPI_SSDTX_NUM=1 +#default CONFIG_ACPI_SSDTX_NUM=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -174,41 +174,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_UNITID_BASE=0x06 #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x01 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -216,10 +216,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x04000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x04000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -230,37 +230,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="MS9185" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="MS9185" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -274,8 +274,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -291,21 +291,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -317,17 +317,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c index cd7a3d236d..aaedd6394b 100644 --- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c @@ -157,7 +157,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -236,7 +236,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; @@ -247,11 +247,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 43cc42fe99..e02de0dc9a 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -105,7 +105,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); if(dev) { m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa=%d\n",m->bus_isa); @@ -121,7 +121,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); if(dev) { m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa=%d\n",m->bus_isa); diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb index 54727bf6ce..056f7ad16c 100644 --- a/src/mainboard/msi/ms9282/Config.lb +++ b/src/mainboard/msi/ms9282/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -41,22 +41,22 @@ driver mainboard.o object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -66,7 +66,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -84,7 +84,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -101,7 +101,7 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -116,7 +116,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb index 1a686826cd..bbcd92e9ca 100644 --- a/src/mainboard/msi/ms9282/Options.lb +++ b/src/mainboard/msi/ms9282/Options.lb @@ -22,79 +22,79 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN #bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE #bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 # stepan 2007-04-12 uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -102,19 +102,19 @@ uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 #1M bytes -#bx- default ROM_SIZE=1048576 +#bx- default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -123,36 +123,36 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -167,22 +167,22 @@ default CONFIG_LOGICAL_CPUS=1 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2 ##bx_b005+ make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #VGA default CONFIG_CONSOLE_VGA=1 @@ -191,15 +191,15 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -209,37 +209,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ms9282" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 +default CONFIG_MAINBOARD_PART_NUMBER="ms9282" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -253,8 +253,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -270,21 +270,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -296,17 +296,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms9282/cache_as_ram_auto.c b/src/mainboard/msi/ms9282/cache_as_ram_auto.c index 6e8760d4bc..7fb3aba1c7 100644 --- a/src/mainboard/msi/ms9282/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9282/cache_as_ram_auto.c @@ -135,7 +135,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -208,7 +208,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ; if (bist == 0) { @@ -240,7 +240,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb index 55d0677c7d..118d61554c 100644 --- a/src/mainboard/nec/powermate2000/Config.lb +++ b/src/mainboard/nec/powermate2000/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/nec/powermate2000/Options.lb b/src/mainboard/nec/powermate2000/Options.lb index 3985c3c067..eae7cb6444 100644 --- a/src/mainboard/nec/powermate2000/Options.lb +++ b/src/mainboard/nec/powermate2000/Options.lb @@ -18,79 +18,79 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 512 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 diff --git a/src/mainboard/nec/powermate2000/auto.c b/src/mainboard/nec/powermate2000/auto.c index 7ce77442ff..507bbbc746 100644 --- a/src/mainboard/nec/powermate2000/auto.c +++ b/src/mainboard/nec/powermate2000/auto.c @@ -45,7 +45,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/nec/powermate2000/irq_tables.c b/src/mainboard/nec/powermate2000/irq_tables.c index bc3113f5f9..b24042df63 100644 --- a/src/mainboard/nec/powermate2000/irq_tables.c +++ b/src/mainboard/nec/powermate2000/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index f5fb2f73a0..f24c351130 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb index 041762eb5f..2766076ea9 100644 --- a/src/mainboard/newisys/khepri/Options.lb +++ b/src/mainboard/newisys/khepri/Options.lb @@ -1,63 +1,63 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -66,50 +66,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -121,7 +121,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -131,9 +131,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -144,37 +144,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Khepri" -default MAINBOARD_VENDOR="Newisys" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 +default CONFIG_MAINBOARD_PART_NUMBER="Khepri" +default CONFIG_MAINBOARD_VENDOR="Newisys" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -188,8 +188,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -206,21 +206,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -232,17 +232,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/newisys/khepri/cache_as_ram_auto.c b/src/mainboard/newisys/khepri/cache_as_ram_auto.c index 6adb906e33..2affa7fbb5 100644 --- a/src/mainboard/newisys/khepri/cache_as_ram_auto.c +++ b/src/mainboard/newisys/khepri/cache_as_ram_auto.c @@ -108,7 +108,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -164,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -194,11 +194,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb index 29725cf8a1..978e88f795 100644 --- a/src/mainboard/nvidia/l1_2pvv/Config.lb +++ b/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,33 +33,33 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt6.c - depends "$(MAINBOARD)/dx/pci6.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci6.asl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex" action "mv pci6.hex ssdt6.c" end object ./ssdt6.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -69,24 +69,24 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -96,13 +96,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -121,8 +121,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -130,7 +130,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -148,13 +148,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -170,12 +170,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb index 2f455f4265..4f032fb7cf 100644 --- a/src/mainboard/nvidia/l1_2pvv/Options.lb +++ b/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -19,90 +19,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -110,9 +110,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -121,21 +121,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -143,40 +143,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -187,25 +187,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -214,16 +214,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -231,15 +231,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -249,37 +249,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="l1_2pvv" -default MAINBOARD_VENDOR="NVIDIA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="l1_2pvv" +default CONFIG_MAINBOARD_VENDOR="NVIDIA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -295,8 +295,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -312,21 +312,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -338,17 +338,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/nvidia/l1_2pvv/apc_auto.c b/src/mainboard/nvidia/l1_2pvv/apc_auto.c index 91c3b5e187..525e940776 100644 --- a/src/mainboard/nvidia/l1_2pvv/apc_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/apc_auto.c @@ -86,8 +86,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c index d2a357da3c..a6a586a1b3 100644 --- a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -152,7 +152,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -220,7 +220,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -233,21 +233,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -260,7 +260,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -271,7 +271,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -291,7 +291,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb index 2f054e3578..c35fb90a69 100644 --- a/src/mainboard/olpc/btest/Config.lb +++ b/src/mainboard/olpc/btest/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/olpc/btest/Options.lb b/src/mainboard/olpc/btest/Options.lb index 70ee04683c..10e30df264 100644 --- a/src/mainboard/olpc/btest/Options.lb +++ b/src/mainboard/olpc/btest/Options.lb @@ -1,51 +1,51 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -54,17 +54,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -74,49 +74,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -126,21 +126,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -152,13 +152,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb index 2f054e3578..c35fb90a69 100644 --- a/src/mainboard/olpc/rev_a/Config.lb +++ b/src/mainboard/olpc/rev_a/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/olpc/rev_a/Options.lb b/src/mainboard/olpc/rev_a/Options.lb index 70ee04683c..10e30df264 100644 --- a/src/mainboard/olpc/rev_a/Options.lb +++ b/src/mainboard/olpc/rev_a/Options.lb @@ -1,51 +1,51 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -54,17 +54,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -74,49 +74,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -126,21 +126,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -152,13 +152,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb index 54021bbccb..0580d746d9 100644 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ b/src/mainboard/pcengines/alix1c/Config.lb @@ -18,8 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -34,14 +34,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -57,7 +57,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb index ea9f3b3a94..2696ab9b1d 100644 --- a/src/mainboard/pcengines/alix1c/Options.lb +++ b/src/mainboard/pcengines/alix1c/Options.lb @@ -18,62 +18,62 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -85,17 +85,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -105,56 +105,56 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 +default CONFIG_PIRQ_ROUTE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -164,21 +164,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -190,13 +190,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c index e7a680cd4d..472ea10c94 100644 --- a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c +++ b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c @@ -161,7 +161,7 @@ void cache_as_ram_main(void) * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c index a7fd6deea7..be03bba2ee 100644 --- a/src/mainboard/pcengines/alix1c/irq_tables.c +++ b/src/mainboard/pcengines/alix1c/irq_tables.c @@ -73,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -83,7 +83,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb index e3defa9a22..ce254cd252 100644 --- a/src/mainboard/rca/rm4100/Config.lb +++ b/src/mainboard/rca/rm4100/Config.lb @@ -18,42 +18,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -63,7 +63,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/rca/rm4100/Options.lb b/src/mainboard/rca/rm4100/Options.lb index 671114b71a..1e3835341b 100644 --- a/src/mainboard/rca/rm4100/Options.lb +++ b/src/mainboard/rca/rm4100/Options.lb @@ -31,71 +31,71 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB -uses CROSS_COMPILE -uses DEFAULT_CONSOLE_LOGLEVEL -uses FALLBACK_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_OPTION_TABLE -uses HAVE_PIRQ_TABLE -uses HEAP_SIZE -uses HOSTCC -uses IRQ_SLOT_COUNT +uses CONFIG_CROSS_COMPILE +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HEAP_SIZE +uses CONFIG_HOSTCC +uses CONFIG_IRQ_SLOT_COUNT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAXIMUM_CONSOLE_LOGLEVEL -uses OBJCOPY -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SIZE -uses STACK_SIZE -uses TTYS0_BASE -uses TTYS0_BAUD -uses TTYS0_LCS -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_OBJCOPY +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_LCS +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 128 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default FALLBACK_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_FALLBACK_SIZE = 512 * 1024 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default HAVE_MP_TABLE = 0 -default HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_IOAPIC = 0 -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x4000 -default _RAMBASE = 0x00004000 -default USE_OPTION_TABLE = 0 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x4000 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = 0 default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_VENDOR = "RCA" -default MAINBOARD_PART_NUMBER = "RM4100" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_VENDOR = "RCA" +default CONFIG_MAINBOARD_PART_NUMBER = "RM4100" # # CBFS # diff --git a/src/mainboard/rca/rm4100/auto.c b/src/mainboard/rca/rm4100/auto.c index b77c05d4da..147c49fe3d 100644 --- a/src/mainboard/rca/rm4100/auto.c +++ b/src/mainboard/rca/rm4100/auto.c @@ -101,7 +101,7 @@ static void main(unsigned long bist) hard_reset(); } - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c index daec6f0274..0ec955126e 100644 --- a/src/mainboard/rca/rm4100/irq_tables.c +++ b/src/mainboard/rca/rm4100/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb index e98657f397..e9e0af931e 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb index 4813e8fdd4..9166a9042a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 0 diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c index c324dc1abf..36e8cd439d 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c index 751c9ee135..22f29e11c3 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router dev */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb index 78235b7e4a..450b293a1c 100644 --- a/src/mainboard/sunw/ultra40/Config.lb +++ b/src/mainboard/sunw/ultra40/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -14,18 +14,18 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -69,7 +69,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -84,7 +84,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb index 4a7e48cdbf..104ff14710 100644 --- a/src/mainboard/sunw/ultra40/Options.lb +++ b/src/mainboard/sunw/ultra40/Options.lb @@ -1,90 +1,90 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -93,36 +93,36 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -134,22 +134,22 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #VGA default CONFIG_CONSOLE_VGA=1 @@ -158,14 +158,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -176,38 +176,38 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ultra40" -default MAINBOARD_VENDOR="sunw" +default CONFIG_MAINBOARD_PART_NUMBER="ultra40" +default CONFIG_MAINBOARD_VENDOR="sunw" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -221,8 +221,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -239,21 +239,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -265,17 +265,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c index bac138cf1f..1514fdaf3f 100644 --- a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c +++ b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c @@ -114,7 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -198,7 +198,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -226,7 +226,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb index c3ad78a215..9c07ae9b6f 100644 --- a/src/mainboard/supermicro/h8dme/Config.lb +++ b/src/mainboard/supermicro/h8dme/Config.lb @@ -16,8 +16,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -30,30 +30,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -63,13 +63,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -88,8 +88,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -97,7 +97,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -115,13 +115,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -137,12 +137,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb index 643cab37cb..d10e4b3304 100644 --- a/src/mainboard/supermicro/h8dme/Options.lb +++ b/src/mainboard/supermicro/h8dme/Options.lb @@ -19,91 +19,91 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -111,9 +111,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -122,24 +122,24 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -#default ROM_SIZE=524288 -default ROM_SIZE=0x100000 +#default CONFIG_ROM_SIZE=524288 +default CONFIG_ROM_SIZE=0x100000 -default HAVE_LOW_TABLES = 0 +default CONFIG_HAVE_LOW_TABLES = 0 default CONFIG_MULTIBOOT=0 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -147,40 +147,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -191,41 +191,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="h8dme" -default MAINBOARD_VENDOR="Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 +default CONFIG_MAINBOARD_PART_NUMBER="h8dme" +default CONFIG_MAINBOARD_VENDOR="Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c index 099b6abd17..442945e9f2 100644 --- a/src/mainboard/supermicro/h8dme/apc_auto.c +++ b/src/mainboard/supermicro/h8dme/apc_auto.c @@ -94,8 +94,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c index a71de8428c..606556ba73 100644 --- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c @@ -35,7 +35,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -53,7 +53,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -72,7 +72,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -194,7 +194,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -263,7 +263,7 @@ normal_image: ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image": /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ ) @@ -275,14 +275,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 -#if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 +#if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -293,7 +293,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #define RC0 (2<<8) #define RC1 (1<<8) -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -315,7 +315,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -326,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); uart_init(); @@ -347,7 +347,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif /* dump_smbus_registers(); */ diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb index 94d91d8810..b8c78b1c9d 100644 --- a/src/mainboard/supermicro/h8dmr/Config.lb +++ b/src/mainboard/supermicro/h8dmr/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb index e65dfca0ed..16c798c2f8 100644 --- a/src/mainboard/supermicro/h8dmr/Options.lb +++ b/src/mainboard/supermicro/h8dmr/Options.lb @@ -19,89 +19,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -109,9 +109,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -120,21 +120,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -#default ROM_SIZE=524288 -default ROM_SIZE=0x100000 +#default CONFIG_ROM_SIZE=524288 +default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,40 +142,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -186,41 +186,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -228,15 +228,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -246,37 +246,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="h8dmr" -default MAINBOARD_VENDOR="Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 +default CONFIG_MAINBOARD_PART_NUMBER="h8dmr" +default CONFIG_MAINBOARD_VENDOR="Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -292,8 +292,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -309,21 +309,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -335,17 +335,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c index 099b6abd17..442945e9f2 100644 --- a/src/mainboard/supermicro/h8dmr/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr/apc_auto.c @@ -94,8 +94,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c index c9b33877b8..34a3bb56eb 100644 --- a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -57,7 +57,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -76,7 +76,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -141,7 +141,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -212,7 +212,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -225,21 +225,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -252,7 +252,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -263,7 +263,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); uart_init(); @@ -278,7 +278,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 2a144eb96a..8acd71c724 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb index 576cdb8c3e..68562efad4 100644 --- a/src/mainboard/supermicro/x6dai_g/Options.lb +++ b/src/mainboard/supermicro/x6dai_g/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DAI" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 +default CONFIG_MAINBOARD_PART_NUMBER="X6DAI" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c index 078296df42..701fcd6484 100644 --- a/src/mainboard/supermicro/x6dai_g/auto.c +++ b/src/mainboard/supermicro/x6dai_g/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index d972ff1ed2..78be06df0b 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture @@ -17,31 +17,31 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb index bd31e7c14c..47eac1d624 100644 --- a/src/mainboard/supermicro/x6dhe_g/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHE_g" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c index da340b73eb..ef99677af7 100644 --- a/src/mainboard/supermicro/x6dhe_g/auto.c +++ b/src/mainboard/supermicro/x6dhe_g/auto.c @@ -102,7 +102,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index 6a284981b0..ea8f3590a5 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -109,7 +109,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } /* PXHd apic 5 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); @@ -121,7 +121,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } } diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index 7a5fcdf933..a4950d33ef 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture @@ -17,31 +17,31 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb index bd31e7c14c..47eac1d624 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHE_g" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c index 0622ab7ade..4a3029f9aa 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c index fcf8b76c19..8de5a2723b 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index 6a284981b0..ea8f3590a5 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -109,7 +109,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } /* PXHd apic 5 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); @@ -121,7 +121,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } } diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 837beb45f4..7d70dcf5db 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c index 92020189d2..722157b454 100644 --- a/src/mainboard/supermicro/x6dhr_ig/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index b223a37523..4aab4fb04b 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c index 7be6250650..97eaca3a63 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb index 8c2f6bc0cb..9ee9be4289 100644 --- a/src/mainboard/technexion/tim8690/Config.lb +++ b/src/mainboard/technexion/tim8690/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/technexion/tim8690/Options.lb b/src/mainboard/technexion/tim8690/Options.lb index d4300898ec..0f8753254d 100644 --- a/src/mainboard/technexion/tim8690/Options.lb +++ b/src/mainboard/technexion/tim8690/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -159,7 +159,7 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -167,23 +167,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -194,39 +194,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="tim8690" -default MAINBOARD_VENDOR="technexion" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="tim8690" +default CONFIG_MAINBOARD_VENDOR="technexion" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -240,8 +240,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -259,21 +259,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -285,21 +285,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb end diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 9aaede4b8d..3829a7a082 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c index 7d60c2703c..3f5ac57fa2 100644 --- a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c +++ b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c @@ -100,7 +100,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -139,14 +139,14 @@ normal_image: fallback_image: post_code(0x25); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -159,7 +159,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { @@ -170,7 +170,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, TTYS0_BASE); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); console_init(); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 9a953ef90d..fb990fd9df 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb index 6d2635770c..525f82e3ef 100644 --- a/src/mainboard/technologic/ts5300/Config.lb +++ b/src/mainboard/technologic/ts5300/Config.lb @@ -1,8 +1,8 @@ -default ROM_SIZE = 128 * 1024 -default FALLBACK_SIZE = 0x10000 +default CONFIG_ROM_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = 0x10000 -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 32 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 32 * 1024 include /config/nofailovercalculation.lb ## @@ -16,29 +16,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -52,7 +52,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -74,7 +74,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/technologic/ts5300/Options.lb b/src/mainboard/technologic/ts5300/Options.lb index 7f2ad59503..461264a474 100644 --- a/src/mainboard/technologic/ts5300/Options.lb +++ b/src/mainboard/technologic/ts5300/Options.lb @@ -1,75 +1,75 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_USE_INIT -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x2f8 +default CONFIG_TTYS0_BASE=0x2f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -78,63 +78,63 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" # # CBFS diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 3ce22f0e9e..343dbdf73c 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -142,7 +142,7 @@ static void enable_dev(struct device *dev) { /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x09400000 + 0xe0000; - rom_end = rom_start + PAYLOAD_SIZE - 1; + rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; printk_err("TS5300 EXIT %s\n", __func__); diff --git a/src/mainboard/televideo/tc7020/Config.lb b/src/mainboard/televideo/tc7020/Config.lb index 8d552d6992..66b1914ef7 100644 --- a/src/mainboard/televideo/tc7020/Config.lb +++ b/src/mainboard/televideo/tc7020/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/televideo/tc7020/Options.lb b/src/mainboard/televideo/tc7020/Options.lb index f215c5a622..96f8739ccc 100644 --- a/src/mainboard/televideo/tc7020/Options.lb +++ b/src/mainboard/televideo/tc7020/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -73,36 +73,36 @@ default CONFIG_GX1_VIDEO = 1 default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default HAVE_PIRQ_TABLE=0 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=0 +default CONFIG_PIRQ_ROUTE=1 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "TeleVideo" -default MAINBOARD_PART_NUMBER = "TC7020" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "TeleVideo" +default CONFIG_MAINBOARD_PART_NUMBER = "TC7020" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/televideo/tc7020/auto.c b/src/mainboard/televideo/tc7020/auto.c index 9880011670..51d847b976 100644 --- a/src/mainboard/televideo/tc7020/auto.c +++ b/src/mainboard/televideo/tc7020/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/televideo/tc7020/irq_tables.c b/src/mainboard/televideo/tc7020/irq_tables.c index d31fa17700..f8af382b22 100644 --- a/src/mainboard/televideo/tc7020/irq_tables.c +++ b/src/mainboard/televideo/tc7020/irq_tables.c @@ -48,7 +48,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* There can be a total of IRQ_SLOT_COUNT devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be a total of CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb index 8177b80e5f..59e4f7705c 100644 --- a/src/mainboard/thomson/ip1000/Config.lb +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -18,42 +18,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -63,7 +63,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/thomson/ip1000/Options.lb b/src/mainboard/thomson/ip1000/Options.lb index 2efa484bbf..b80c53f2d8 100644 --- a/src/mainboard/thomson/ip1000/Options.lb +++ b/src/mainboard/thomson/ip1000/Options.lb @@ -31,71 +31,71 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB -uses CROSS_COMPILE -uses DEFAULT_CONSOLE_LOGLEVEL -uses FALLBACK_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_OPTION_TABLE -uses HAVE_PIRQ_TABLE -uses HEAP_SIZE -uses HOSTCC -uses IRQ_SLOT_COUNT +uses CONFIG_CROSS_COMPILE +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HEAP_SIZE +uses CONFIG_HOSTCC +uses CONFIG_IRQ_SLOT_COUNT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAXIMUM_CONSOLE_LOGLEVEL -uses OBJCOPY -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SIZE -uses STACK_SIZE -uses TTYS0_BASE -uses TTYS0_BAUD -uses TTYS0_LCS -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_OBJCOPY +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_LCS +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 128 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default FALLBACK_SIZE = 256 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_FALLBACK_SIZE = 256 * 1024 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default HAVE_MP_TABLE = 0 -default HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_IOAPIC = 0 -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x4000 -default _RAMBASE = 0x00004000 -default USE_OPTION_TABLE = 0 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x4000 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = 0 default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_VENDOR = "THOMSON" -default MAINBOARD_PART_NUMBER = "IP1000" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_VENDOR = "THOMSON" +default CONFIG_MAINBOARD_PART_NUMBER = "IP1000" # # CBFS # diff --git a/src/mainboard/thomson/ip1000/auto.c b/src/mainboard/thomson/ip1000/auto.c index 8760f89d6f..9c31db5bcd 100644 --- a/src/mainboard/thomson/ip1000/auto.c +++ b/src/mainboard/thomson/ip1000/auto.c @@ -101,7 +101,7 @@ static void main(unsigned long bist) hard_reset(); } - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c index daec6f0274..0ec955126e 100644 --- a/src/mainboard/thomson/ip1000/irq_tables.c +++ b/src/mainboard/thomson/ip1000/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb index 968471c553..c380a86848 100644 --- a/src/mainboard/totalimpact/briq/Config.lb +++ b/src/mainboard/totalimpact/briq/Config.lb @@ -46,4 +46,4 @@ end ## Build the objects we have code for in this directory. ## -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb index 3a06b57be5..07c18e1eed 100644 --- a/src/mainboard/totalimpact/briq/Options.lb +++ b/src/mainboard/totalimpact/briq/Options.lb @@ -2,77 +2,77 @@ ## Config file for the Total Impact briQ ## -uses TTYS0_DIV +uses CONFIG_TTYS0_DIV uses CONFIG_CBFS uses CONFIG_ARCH_X86 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_BRIQ_750FX uses CONFIG_BRIQ_7400 -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses _IO_BASE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_IO_BASE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_IDE_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses IDE_BOOT_DRIVE -uses IDE_SWAB IDE_OFFSET -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE +uses CONFIG_IDE_BOOT_DRIVE +uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE uses CONFIG_BRIQ_750FX uses CONFIG_BRIQ_7400 uses CONFIG_SYS_CLK_FREQ -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0x80000000 -default ISA_MEM_BASE=0xc0000000 -default PCIC0_CFGADDR=0xff5f8000 -default PCIC0_CFGDATA=0xff5f8010 -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0x80000000 +default CONFIG_ISA_MEM_BASE=0xc0000000 +default CONFIG_PCIC0_CFGADDR=0xff5f8000 +default CONFIG_PCIC0_CFGDATA=0xff5f8010 +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The briQ uses weird clocking, 4 = 115200 ## -default TTYS0_DIV=4 +default CONFIG_TTYS0_DIV=4 ## ## Set UART base address ## -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -82,24 +82,24 @@ default CONFIG_USE_INIT=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 ## Boot linux from IDE default CONFIG_IDE_PAYLOAD=1 -default IDE_BOOT_DRIVE=0 -default IDE_SWAB=1 -default IDE_OFFSET=0 +default CONFIG_IDE_BOOT_DRIVE=0 +default CONFIG_IDE_SWAB=1 +default CONFIG_IDE_OFFSET=0 # ROM is 1Mb -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 ## ## System clock @@ -108,21 +108,21 @@ default CONFIG_SYS_CLK_FREQ=33 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 default CONFIG_BRIQ_750FX=1 #default CONFIG_BRIQ_7400=1 diff --git a/src/mainboard/totalimpact/briq/init.c b/src/mainboard/totalimpact/briq/init.c index fd9283d37a..b7edf0b7e9 100644 --- a/src/mainboard/totalimpact/briq/init.c +++ b/src/mainboard/totalimpact/briq/init.c @@ -41,7 +41,7 @@ board_init2(void) /* * Enable UART */ - uart8250_init(TTYS0_BASE, TTYS0_DIV, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, CONFIG_TTYS0_LCS); printk_info("briQ initialized...\n"); } diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb index 1cfed3286a..828db296ed 100644 --- a/src/mainboard/tyan/s1846/Config.lb +++ b/src/mainboard/tyan/s1846/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb index e5ebc85be6..9f3680c391 100644 --- a/src/mainboard/tyan/s1846/Options.lb +++ b/src/mainboard/tyan/s1846/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c index 17ab6b02ed..5720e6709d 100644 --- a/src/mainboard/tyan/s1846/auto.c +++ b/src/mainboard/tyan/s1846/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index f051c5f352..9cc0bc3aea 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -10,21 +10,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -49,7 +49,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -73,7 +73,7 @@ mainboardinit cpu/x86/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index b52c94b734..7a5d39b0a5 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -1,82 +1,82 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_USE_INIT uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +#default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ### ### Build options @@ -85,12 +85,12 @@ default FALLBACK_SIZE=131072 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## Delay timer options ## @@ -100,26 +100,26 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -130,7 +130,7 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -142,10 +142,10 @@ default SERIAL_CPU_INIT=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xF2000000 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +#default CONFIG_DCACHE_RAM_BASE=0xF2000000 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_PRINTK_IN_CAR=1 @@ -157,37 +157,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2735" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 +default CONFIG_MAINBOARD_PART_NUMBER="s2735" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -201,8 +201,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -217,21 +217,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -243,17 +243,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c index 8c4a0370e0..427b070bdb 100644 --- a/src/mainboard/tyan/s2735/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c @@ -79,7 +79,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/x86/car/copy_and_run.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801er/cmos_failover.c" @@ -147,7 +147,7 @@ void amd64_main(unsigned long bist) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -228,10 +228,10 @@ cpu_reset_x: } __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) ); { diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 84bb7084eb..59dcd8e557 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index f9317f7bd2..37814240be 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=12 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=12 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2850" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 +default CONFIG_MAINBOARD_PART_NUMBER="S2850" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index 373e0a6192..378c05a723 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -94,7 +94,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -150,7 +150,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -179,7 +179,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index bb3393fe3c..73481883f8 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb index 01daaa4e6f..5eaa91acc6 100644 --- a/src/mainboard/tyan/s2875/Options.lb +++ b/src/mainboard/tyan/s2875/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,51 +67,51 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -123,7 +123,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -133,9 +133,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -146,37 +146,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2875" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 +default CONFIG_MAINBOARD_PART_NUMBER="s2875" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -190,8 +190,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -208,21 +208,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -234,17 +234,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2875/cache_as_ram_auto.c b/src/mainboard/tyan/s2875/cache_as_ram_auto.c index 893635b9f8..1912beeeb8 100644 --- a/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -85,7 +85,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -138,7 +138,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -176,7 +176,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 85ade62c85..3ca46b67bb 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb index 8b37f911db..0a1c746f20 100644 --- a/src/mainboard/tyan/s2880/Options.lb +++ b/src/mainboard/tyan/s2880/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2880" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 +default CONFIG_MAINBOARD_PART_NUMBER="S2880" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c index eb4bcae466..bfb89116c6 100644 --- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -138,7 +138,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -177,7 +177,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index f9ac2a2570..6480067300 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb index d83638715b..18087be3d3 100644 --- a/src/mainboard/tyan/s2881/Options.lb +++ b/src/mainboard/tyan/s2881/Options.lb @@ -1,69 +1,69 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -72,50 +72,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -127,19 +127,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0a +default CONFIG_HT_CHAIN_UNITID_BASE=0x0a ##real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=0 +default CONFIG_SB_HT_CHAIN_ON_BUS0=0 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -149,9 +149,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -162,37 +162,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2881" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 +default CONFIG_MAINBOARD_PART_NUMBER="s2881" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -206,8 +206,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -224,21 +224,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -250,17 +250,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 0f853b8af1..9beb7afaeb 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -99,7 +99,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,7 +185,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index d4c01675ab..1ed1e0dbaa 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -82,7 +82,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -105,7 +105,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index c61a0f3291..687169622a 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb index 9e6b36db70..cfa2b679b9 100644 --- a/src/mainboard/tyan/s2882/Options.lb +++ b/src/mainboard/tyan/s2882/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2882" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 +default CONFIG_MAINBOARD_PART_NUMBER="S2882" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index a249fa1a8d..62d9a69d10 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -141,7 +141,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -180,7 +180,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 9ee230a90e..74f9c53e65 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 88e7bf2790..2bb6681057 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -1,75 +1,75 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK @@ -78,50 +78,50 @@ uses CONFIG_LB_MEM_TOPK ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -133,19 +133,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0a +default CONFIG_HT_CHAIN_UNITID_BASE=0x0a ##real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -155,14 +155,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -172,37 +172,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2885" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 +default CONFIG_MAINBOARD_PART_NUMBER="s2885" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -216,8 +216,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -234,21 +234,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -260,17 +260,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 711afbc645..c2f97df8ae 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -99,7 +99,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,11 +185,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index b50f671f9b..eaf77cd569 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -85,7 +85,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -108,7 +108,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index d1a3874435..f14894d23e 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -16,15 +16,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -34,13 +34,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -49,7 +49,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -84,7 +84,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -99,7 +99,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index ed514efc1d..d3cc2c2eff 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -1,96 +1,96 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=512*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -99,48 +99,48 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -157,19 +157,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -181,14 +181,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -201,37 +201,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2891" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 +default CONFIG_MAINBOARD_PART_NUMBER="s2891" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -245,8 +245,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -263,21 +263,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -289,17 +289,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index 6cf98abeb5..fd6c1c5236 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -77,7 +77,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -165,7 +165,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -195,7 +195,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index 45672e99c6..04a53b57be 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -17,15 +17,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -35,13 +35,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -50,7 +50,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -68,7 +68,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -100,7 +100,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 0cfbcd5c56..efc4cba7a5 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -1,90 +1,90 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=1024*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=1024*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -93,48 +93,48 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -151,19 +151,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -175,9 +175,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 @@ -189,37 +189,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2892" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 +default CONFIG_MAINBOARD_PART_NUMBER="s2892" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -233,8 +233,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -251,21 +251,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -277,17 +277,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index bafd6e9c9b..97f0660096 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -83,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,7 +185,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index a8023fe0c7..3bf256f3e3 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -12,15 +12,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -30,13 +30,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -45,13 +45,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -70,8 +70,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -97,13 +97,13 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -119,12 +119,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 19c7cdfd73..58878494cd 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -1,103 +1,103 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses USE_FAILOVER_IMAGE -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=1024*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=1024*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -105,49 +105,49 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -163,25 +163,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -190,14 +190,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -208,37 +208,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2895" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 +default CONFIG_MAINBOARD_PART_NUMBER="s2895" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -252,8 +252,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -270,21 +270,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -296,17 +296,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index 43a6cf089e..2da764f24e 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -21,7 +21,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -44,7 +44,7 @@ #define SUPERIO_GPIO_IO_BASE 0x400 -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -120,7 +120,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -197,7 +197,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) fallback_image: // post_code(0x25); -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -211,21 +211,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -250,7 +250,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb index 34638892ae..c8f3a8f041 100644 --- a/src/mainboard/tyan/s2912/Config.lb +++ b/src/mainboard/tyan/s2912/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb index 7222788349..a2166dd8b0 100644 --- a/src/mainboard/tyan/s2912/Options.lb +++ b/src/mainboard/tyan/s2912/Options.lb @@ -19,90 +19,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -110,9 +110,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -121,21 +121,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -143,42 +143,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## extra SSDT num -default ACPI_SSDTX_NUM=3 +default CONFIG_ACPI_SSDTX_NUM=3 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -189,25 +189,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -216,16 +216,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2912" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 +default CONFIG_MAINBOARD_PART_NUMBER="S2912" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2912/apc_auto.c b/src/mainboard/tyan/s2912/apc_auto.c index d15f5ac346..8985b7affd 100644 --- a/src/mainboard/tyan/s2912/apc_auto.c +++ b/src/mainboard/tyan/s2912/apc_auto.c @@ -75,8 +75,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912/cache_as_ram_auto.c b/src/mainboard/tyan/s2912/cache_as_ram_auto.c index 7c387b9bd0..5be6d82e9b 100644 --- a/src/mainboard/tyan/s2912/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -150,7 +150,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -219,7 +219,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -232,21 +232,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -259,7 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); @@ -287,7 +287,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb index 2e66e5a470..26977d657d 100644 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ b/src/mainboard/tyan/s2912_fam10/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb index 0f77329e6b..5d250e82a4 100644 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ b/src/mainboard/tyan/s2912_fam10/Options.lb @@ -19,125 +19,125 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK -uses PCI_BUS_SEGN_BITS +uses CONFIG_PCI_BUS_SEGN_BITS uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CAR_FAM10 -uses AMD_UCODE_PATCH_FILE +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=1024*1024 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 -default FALLBACK_SIZE=0x3f000 -default FAILOVER_SIZE=0x01000 +default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=16384 @@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## extra SSDT num -default ACPI_SSDTX_NUM=31 +default CONFIG_ACPI_SSDTX_NUM=31 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -191,22 +191,22 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x00 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -215,16 +215,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=1 +default CONFIG_HT_CHAIN_UNITID_BASE=1 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -232,14 +232,14 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 default CONFIG_USE_INIT=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 default CONFIG_AMDMCT = 1 ## @@ -250,10 +250,10 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2912 (Fam10)" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 +default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ## ## Set microcode patch file name @@ -263,34 +263,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" ## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0xc0000 +default CONFIG_HEAP_SIZE=0xc0000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00200000 +default CONFIG_RAMBASE=0x00200000 ## ## Load the payload from the ROM @@ -306,8 +306,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -323,21 +323,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -349,17 +349,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2912_fam10/apc_auto.c b/src/mainboard/tyan/s2912_fam10/apc_auto.c index d15f5ac346..8985b7affd 100644 --- a/src/mainboard/tyan/s2912_fam10/apc_auto.c +++ b/src/mainboard/tyan/s2912_fam10/apc_auto.c @@ -75,8 +75,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c index 8121d34bf7..ffdf04a92b 100644 --- a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c @@ -53,7 +53,7 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -75,7 +75,7 @@ static void post_code(u8 value) { #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -145,7 +145,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -215,7 +215,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -228,28 +228,28 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; @@ -264,7 +264,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk_debug("\n"); diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index 86fa65f2c2..ea870a147b 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -111,11 +111,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; } -#if CBB - write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if(sysconf.nodes>32) { - write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #endif diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 73d3d43014..b638d4f718 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ static void setup_mb_resource_map(void) * This field defines the upp adddress bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, -// PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, -// PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index eacd638313..c85db4b9b2 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -11,21 +11,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -76,7 +76,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index 485ab8397b..05760e668c 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -1,120 +1,120 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=22 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=22 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -126,7 +126,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -136,14 +136,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -154,37 +154,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PART_NUMBER="s4880" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PART_NUMBER="s4880" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -198,8 +198,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -216,21 +216,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -242,17 +242,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index d7226afcef..0f403ab6ba 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -112,7 +112,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -164,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -226,7 +226,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 97bf1e06b6..7da0a6773a 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -11,21 +11,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -76,7 +76,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index e5eadf414f..3ae897bb7c 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -1,120 +1,120 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=22 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=22 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -126,7 +126,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 @@ -136,14 +136,14 @@ default HW_MEM_HOLE_SIZEK=0x100000 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -153,37 +153,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PART_NUMBER="s4882" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PART_NUMBER="s4882" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00002000 +default CONFIG_RAMBASE=0x00002000 ## ## Load the payload from the ROM @@ -197,8 +197,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -215,21 +215,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -241,17 +241,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index cdc1d2645f..b45e1dc467 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -119,7 +119,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -171,7 +171,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -206,7 +206,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb index c2f5a4ebc0..5e3149eb7e 100644 --- a/src/mainboard/via/epia-cn/Config.lb +++ b/src/mainboard/via/epia-cn/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/epia-cn/Options.lb b/src/mainboard/via/epia-cn/Options.lb index 77ec483dd7..b80f2a3277 100644 --- a/src/mainboard/via/epia-cn/Options.lb +++ b/src/mainboard/via/epia-cn/Options.lb @@ -19,83 +19,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 9 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 9 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c index fc63ff1c32..2b6607b1ec 100644 --- a/src/mainboard/via/epia-cn/irq_tables.c +++ b/src/mainboard/via/epia-cn/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb index 228a0265ba..8bb51b639b 100644 --- a/src/mainboard/via/epia-m/Config.lb +++ b/src/mainboard/via/epia-m/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,11 +13,11 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o object vgabios.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o @@ -27,22 +27,22 @@ end ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -56,7 +56,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -78,7 +78,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb index 5781156c49..aeb9521c0b 100644 --- a/src/mainboard/via/epia-m/Options.lb +++ b/src/mainboard/via/epia-m/Options.lb @@ -1,54 +1,54 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -59,12 +59,12 @@ default CONFIG_CONSOLE_VGA=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Use TSC for udelay. @@ -75,60 +75,60 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 ## ## Build code to load acpi tables ## -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Set this to the max PCI bus number you @@ -139,8 +139,8 @@ default HOSTCC="gcc" ## default CONFIG_MAX_PCI_BUSES = 5 -default MAXIMUM_CONSOLE_LOGLEVEL=8 -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb index 70f669ef62..33006e4963 100644 --- a/src/mainboard/via/epia-m700/Config.lb +++ b/src/mainboard/via/epia-m700/Config.lb @@ -18,16 +18,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o driver wakeup.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o # object ssdt.o @@ -35,23 +35,23 @@ if HAVE_ACPI_TABLES end # These lines maybe noused. makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end @@ -65,7 +65,7 @@ ldscript /northbridge/via/vx800/romstrap.lds mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,11 +81,11 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM mainboardinit cpu/via/car/cache_as_ram.inc end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # failover.inc need definition in cpu_reset.inc, but we do not include # cpu_reset.inc,so ... @@ -94,7 +94,7 @@ end # mainboardinit cpu/x86/fpu/enable_fpu.inc # mainboardinit cpu/x86/mmx/enable_mmx.inc -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb index 5fe9240778..c0fc338df5 100644 --- a/src/mainboard/via/epia-m700/Options.lb +++ b/src/mainboard/via/epia-m700/Options.lb @@ -18,59 +18,59 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC ## New options -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT #uses MAX_RAM_SLOTS #uses USB_ENABLE @@ -85,11 +85,11 @@ uses CONFIG_USE_INIT #uses VIACONFIG_VGA_PCI_14 ## New options -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xffef0000 -# default DCACHE_RAM_BASE = 0xffbf0000 -# default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. -default DCACHE_RAM_SIZE = 8 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xffef0000 +# default CONFIG_DCACHE_RAM_BASE = 0xffbf0000 +# default CONFIG_DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. +default CONFIG_DCACHE_RAM_SIZE = 8 * 1024 default CONFIG_USE_INIT = 0 #default MAX_RAM_SLOTS = 2 #default USB_ENABLE = 1 @@ -104,7 +104,7 @@ default CONFIG_USE_INIT = 0 #default VIACONFIG_VGA_PCI_10 = 0xf8000008 #default VIACONFIG_VGA_PCI_14 = 0xfc000000 -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 1 # Define framebuffer size of VX800's integrated graphics card. @@ -114,27 +114,27 @@ default CONFIG_VIDEO_MB = 64 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 14 -default HAVE_ACPI_TABLES = 1 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 128 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 16 * 1024 -default HEAP_SIZE = 20 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 14 +default CONFIG_HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 16 * 1024 +default CONFIG_HEAP_SIZE = 20 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CBFS = 0 ## diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c index 54480cdff5..709af4b65e 100644 --- a/src/mainboard/via/epia-m700/acpi_tables.c +++ b/src/mainboard/via/epia-m700/acpi_tables.c @@ -43,9 +43,9 @@ extern u8 acpi_sleep_type; /* * These four macros are copied from <arch/smp/mpspec.h>, I have to do this - * since the "default HAVE_MP_TABLE = 0" in Options.lb, and also since + * since the "default CONFIG_HAVE_MP_TABLE = 0" in Options.lb, and also since * mainboard/via/... have no mptable.c (so that I can not set - * HAVE_MP_TABLE = 1) as many other mainboards. + * CONFIG_HAVE_MP_TABLE = 1) as many other mainboards. * So I have to copy these four to here. acpi_fill_madt() needs this. */ #define MP_IRQ_POLARITY_HIGH 0x1 diff --git a/src/mainboard/via/epia-m700/cache_as_ram_auto.c b/src/mainboard/via/epia-m700/cache_as_ram_auto.c index 82683a5bdc..de5acb90bd 100644 --- a/src/mainboard/via/epia-m700/cache_as_ram_auto.c +++ b/src/mainboard/via/epia-m700/cache_as_ram_auto.c @@ -708,7 +708,7 @@ void amd64_main(unsigned long bist) * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c". * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my - * $XIP_ROM_BASE+SIZE area. + * $CONFIG_XIP_ROM_BASE+SIZE area. * * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have * some diff with x86-version. @@ -772,10 +772,10 @@ cpu_reset_x: #include "cpu/via/car/cache_as_ram_post.c" /* #include "cpu/x86/car/cache_as_ram_post.c" */ __asm__ volatile ( - /* Set new esp *//* before _RAMBASE */ + /* Set new esp *//* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t":: - "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - _RAMBASE) + "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE) ); { diff --git a/src/mainboard/via/epia-m700/irq_tables.c b/src/mainboard/via/epia-m700/irq_tables.c index cb841bf1e4..817b4d6130 100644 --- a/src/mainboard/via/epia-m700/irq_tables.c +++ b/src/mainboard/via/epia-m700/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index 47b957608a..40d88f943e 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,29 +13,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -49,7 +49,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -71,7 +71,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end @@ -132,7 +132,7 @@ chip northbridge/via/vt8601 irq 0x70 = 1 irq 0x72 = 12 end - register "com1" = "{TTYS0_BAUD}" + register "com1" = "{CONFIG_TTYS0_BAUD}" end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb index 6e4856c543..dd1bfb0753 100644 --- a/src/mainboard/via/epia/Options.lb +++ b/src/mainboard/via/epia/Options.lb @@ -1,70 +1,70 @@ -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CBFS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_UDELAY_IO uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY # logging -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL # logging -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 +default CONFIG_TTYS0_BAUD=115200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -73,17 +73,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## use io based udelay function @@ -96,49 +96,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb index 405863a456..93ea99b489 100644 --- a/src/mainboard/via/pc2500e/Config.lb +++ b/src/mainboard/via/pc2500e/Config.lb @@ -18,40 +18,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb index c19f2cd529..ee217383e5 100644 --- a/src/mainboard/via/pc2500e/Options.lb +++ b/src/mainboard/via/pc2500e/Options.lb @@ -20,97 +20,97 @@ uses CONFIG_SMP uses CONFIG_CBFS -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_SMP = 1 -default HAVE_MP_TABLE = 1 +default CONFIG_HAVE_MP_TABLE = 1 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default USE_FALLBACK_IMAGE = 1 -default MAINBOARD_VENDOR = "VIA" -default MAINBOARD_PART_NUMBER = "pc2500e" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 1 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_MAINBOARD_VENDOR = "VIA" +default CONFIG_MAINBOARD_PART_NUMBER = "pc2500e" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 1 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" default CONFIG_MAX_PCI_BUSES = 3 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # diff --git a/src/mainboard/via/pc2500e/auto.c b/src/mainboard/via/pc2500e/auto.c index dbc6720607..f11dacd778 100644 --- a/src/mainboard/via/pc2500e/auto.c +++ b/src/mainboard/via/pc2500e/auto.c @@ -65,7 +65,7 @@ static void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - it8716f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c index a9f39ac54d..71d7ba0ef8 100644 --- a/src/mainboard/via/pc2500e/irq_tables.c +++ b/src/mainboard/via/pc2500e/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb index 534f910b19..9860ba6676 100644 --- a/src/mainboard/via/vt8454c/Config.lb +++ b/src/mainboard/via/vt8454c/Config.lb @@ -19,8 +19,8 @@ ## MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -35,20 +35,20 @@ arch i386 end driver mainboard.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -58,8 +58,8 @@ end ## Romcc output ## makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -75,7 +75,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb index 3f1bdb768b..d9ba74c01b 100644 --- a/src/mainboard/via/vt8454c/Options.lb +++ b/src/mainboard/via/vt8454c/Options.lb @@ -19,57 +19,57 @@ ## MA 02110-1301 USA ## -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses IRQ_SLOT_COUNT -uses HAVE_ACPI_TABLES -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses HAVE_LOW_TABLES - -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_HAVE_LOW_TABLES + +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE uses CONFIG_CBFS # compiler specifics -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY # Console specifics -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -81,19 +81,19 @@ uses CONFIG_IOAPIC uses CONFIG_GDB_STUB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xffef0000 -#default DCACHE_RAM_BASE=0xffbf0000 -#default DCACHE_RAM_BASE=0xfec00000 -default DCACHE_RAM_SIZE=0x8000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xffef0000 +#default CONFIG_DCACHE_RAM_BASE=0xffbf0000 +#default CONFIG_DCACHE_RAM_BASE=0xfec00000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 default CONFIG_USE_PRINTK_IN_CAR=1 ### @@ -105,7 +105,7 @@ default CONFIG_CONSOLE_VGA=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Use TSC for udelay. @@ -116,34 +116,34 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to load acpi tables ## -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Build code to fill in tables both in low and high memory ## -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 ## @@ -156,36 +156,36 @@ default CONFIG_IOAPIC=1 ### LinuxBIOS layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = ROM_IMAGE_SIZE +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Set this to the max PCI bus number you @@ -209,21 +209,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ## Select the coreboot loglevel @@ -235,13 +235,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 # # CBFS diff --git a/src/mainboard/via/vt8454c/irq_tables.c b/src/mainboard/via/vt8454c/irq_tables.c index 40d1ebb691..fffce3170d 100644 --- a/src/mainboard/via/vt8454c/irq_tables.c +++ b/src/mainboard/via/vt8454c/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* There can be total 15 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 15 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ |