summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 346a3096b6..37bb8f23c2 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -11,13 +11,14 @@ chip soc/intel/tigerlake
# - GPP_B3 - TRACKPAD_INT_ODL
# - GPP_B4 - H1_AP_INT_ODL
# DW1 is used by:
- # - GPP_D3 - WLAN_PCIE_WAKE_ODL
+ # - GPP_C12 - AP_PEN_DET_ODL
# DW2 is used by:
- # - GPP_H16 - WWAN_HOST_WAKE
+ # - GPP_D0 - WWAN_HOST_WAKE
+ # - GPP_D3 - WLAN_PCIE_WAKE_ODL
# EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
register "pmc_gpe0_dw0" = "GPP_B"
- register "pmc_gpe0_dw1" = "GPP_D"
- register "pmc_gpe0_dw2" = "GPP_H"
+ register "pmc_gpe0_dw1" = "GPP_C"
+ register "pmc_gpe0_dw2" = "GPP_D"
# USB Port Configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0