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-rw-r--r--src/mainboard/asrock/g41c-gs/Kconfig8
-rw-r--r--src/mainboard/asrock/g41c-gs/Kconfig.name3
-rw-r--r--src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl39
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb139
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c118
5 files changed, 305 insertions, 2 deletions
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig
index 3eb0023426..3ade4207d3 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig
+++ b/src/mainboard/asrock/g41c-gs/Kconfig
@@ -14,7 +14,8 @@
# GNU General Public License for more details.
#
-if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS
+if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS \
+ || BOARD_ASROCK_G41M_VS3_R2_0
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -24,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \
- || BOARD_ASROCK_G41M_GS
+ || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select PCIEXP_ASPM
@@ -46,18 +47,21 @@ config VARIANT_DIR
default "g41c-gs-r2" if BOARD_ASROCK_G41C_GS_R2_0
default "g41c-gs" if BOARD_ASROCK_G41C_GS
default "g41m-gs" if BOARD_ASROCK_G41M_GS
+ default "g41m-vs3-r2" if BOARD_ASROCK_G41M_VS3_R2_0
config MAINBOARD_PART_NUMBER
string
default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
default "G41C-GS" if BOARD_ASROCK_G41C_GS
default "G41M-GS" if BOARD_ASROCK_G41M_GS
+ default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0
config DEVICETREE
string
default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS
+ default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0
config MAX_CPUS
int
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name
index 329a3e20eb..e10558c053 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig.name
+++ b/src/mainboard/asrock/g41c-gs/Kconfig.name
@@ -6,3 +6,6 @@ config BOARD_ASROCK_G41C_GS
config BOARD_ASROCK_G41M_GS
bool "G41M-GS"
+
+config BOARD_ASROCK_G41M_VS3_R2_0
+ bool "G41M-VS3 R2.0"
diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
index bb8745ee97..09d961d2b4 100644
--- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
@@ -18,6 +18,44 @@
* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
*/
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)
+If (PICM) {
+ Return (Package() {
+ /* PCI1 SLOT 1 */
+ Package() { 0x0000ffff, 0, 0, 0x11},
+ Package() { 0x0000ffff, 1, 0, 0x12},
+ Package() { 0x0000ffff, 2, 0, 0x13},
+ Package() { 0x0000ffff, 3, 0, 0x10},
+
+ /* PCI1 SLOT 2 */
+ Package() { 0x0002ffff, 0, 0, 0x17},
+ Package() { 0x0002ffff, 1, 0, 0x14},
+ Package() { 0x0002ffff, 2, 0, 0x15},
+ Package() { 0x0002ffff, 3, 0, 0x16},
+
+ /* device not in lspci but in vendor DSDT */
+ /* Package() { 0x0008ffff, 0, 0, 0x14}, */
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+ /* device not in lspci but in vendor DSDT */
+ /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */
+ })
+}
+#else
+/* IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) \
+ || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) \
+ || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) */
If (PICM) {
Return (Package() {
/* PCI1 SLOT 1 */
@@ -51,3 +89,4 @@ If (PICM) {
/* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */
})
}
+#endif
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
new file mode 100644
index 0000000000..6e47ea942f
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
@@ -0,0 +1,139 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x1458 0x5000 inherit
+ device pci 0.0 on # Host Bridge
+ subsystemid 0x1849 0x2e30
+ end
+ device pci 1.0 on end # PEG
+
+ device pci 2.0 on # Integrated graphics controller
+ subsystemid 0x1849 0x2e32
+ end
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801gx # Southbridge
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x0b"
+
+ register "ide_enable_primary" = "0x1"
+ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
+ register "gpe0_en" = "0x440"
+
+ device pci 1b.0 on # Audio
+ subsystemid 0x1849 0x3662
+ end
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2 (ethernet)
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on # USB
+ subsystemid 0x1849 0x27c8
+ end
+ device pci 1d.1 on # USB
+ subsystemid 0x1849 0x27c9
+ end
+ device pci 1d.2 on # USB
+ subsystemid 0x1849 0x27ca
+ end
+ device pci 1d.3 on # USB
+ subsystemid 0x1849 0x27cb
+ end
+ device pci 1d.7 on # USB
+ subsystemid 0x1849 0x27cc
+ end
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 off end # AC'97 Audio
+ device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # ISA bridge
+ subsystemid 0x1849 0x27b8
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel port
+ # global
+ irq 0x28 = 0x70
+ irq 0x2c = 0xd2
+ # parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2
+ device pnp 2e.5 on # Keyboard & MOUSE
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 0x0C
+ end
+ device pnp 2e.6 off end # SPI
+ device pnp 2e.7 off end # GPIO6
+ device pnp 2e.8 off end # WDT0#, PLED
+ device pnp 2e.9 on end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 on # GPIO4
+ irq 0xf4 = 0xb3
+ end
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.a on # ACPI
+ irq 0xe4 = 0x10 # Power dram during s3
+ end
+ device pnp 2e.b on # HWM, front panel LED
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ device pnp 2e.c off end # PECI, SST
+ end
+ end
+ device pci 1f.1 on # PATA/IDE
+ subsystemid 0x1849 0x27df
+ end
+ device pci 1f.2 on # SATA
+ subsystemid 0x1849 0x27c0
+ end
+ device pci 1f.3 on # SMbus
+ subsystemid 0x1849 0x27da
+ chip drivers/i2c/ck505 # W83115RG-965
+ # set SATA to fixed 100Mhz refclk
+ register "mask" = "{ 0x02 }"
+ register "regs" = "{ 0x02 }"
+ device i2c 69 on end
+ end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c
new file mode 100644
index 0000000000..c67571b45b
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+};
+
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 17:25:14 +0000