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-rw-r--r--src/mainboard/google/poppy/acpi/dptf.asl83
-rw-r--r--src/mainboard/google/poppy/devicetree.cb4
-rw-r--r--src/mainboard/google/poppy/dsdt.asl6
3 files changed, 93 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl
new file mode 100644
index 0000000000..7f6cd8e722
--- /dev/null
+++ b/src/mainboard/google/poppy/acpi/dptf.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 94
+#define DPTF_CPU_CRITICAL 99
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Ambient"
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "Charger"
+#define DPTF_TSR1_PASSIVE 55
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "DRAM"
+#define DPTF_TSR2_PASSIVE 52
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 4500, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 3000, /* PowerLimitMinimum */
+ 7000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 07cacc0500..1f25821f79 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -19,6 +19,9 @@ chip soc/intel/skylake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
@@ -184,6 +187,7 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
register "tdp_pl2_override" = "7"
+ register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_G7"
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index c678dfcf24..2007691a05 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -61,4 +61,10 @@ DefinitionBlock(
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
+
+ Scope (\_SB)
+ {
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
}