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-rw-r--r--src/mainboard/google/lars/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 99522cbe3e..64f2a61f97 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -233,14 +233,14 @@ chip soc/intel/skylake
register "vref_impedance" = "2" # 125kOhm
register "micbias_voltage" = "6" # 2.754
register "sar_threshold_num" = "4"
- register "sar_threshold[0]" = "0x0a"
- register "sar_threshold[1]" = "0x14"
+ register "sar_threshold[0]" = "0x08"
+ register "sar_threshold[1]" = "0x12"
register "sar_threshold[2]" = "0x26"
register "sar_threshold[3]" = "0x73"
register "sar_hysteresis" = "0"
register "sar_voltage" = "6"
- register "sar_compare_time" = "0" # 500ns
- register "sar_sampling_time" = "0" # 2us
+ register "sar_compare_time" = "1" # 1us
+ register "sar_sampling_time" = "1" # 4us
register "short_key_debounce" = "3" # 30ms
register "jack_insert_debounce" = "7" # 512ms
register "jack_eject_debounce" = "0"