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-rw-r--r--src/mainboard/google/volteer/dsdt.asl6
-rw-r--r--src/mainboard/google/volteer/mainboard.asl48
2 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index af881ae859..450835db03 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -32,11 +32,17 @@ DefinitionBlock(
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
}
+ /* Mainboard hooks */
+ #include "mainboard.asl"
}
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+ /* Include Low power idle table for a short term workaround to enable
+ S0ix. Once cr50 pulse width is fixed, this can be removed. */
+ #include <soc/intel/common/acpi/lpit.asl>
+
// Chrome OS Embedded Controller
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl
new file mode 100644
index 0000000000..d58822d719
--- /dev/null
+++ b/src/mainboard/google/volteer/mainboard.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+ For (Local0 = 0, Local0 < 6, Local0++)
+ {
+ \_SB.PCI0.CGPM (Local0, Arg0)
+ }
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+ PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+ PGPM (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+ If (Arg0 == 1) {
+ /* S0ix Entry */
+ PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ } Else {
+ /* S0ix Exit */
+ PGPM (0)
+ }
+}