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-rw-r--r--src/mainboard/emulation/qemu-x86/northbridge.c5
-rw-r--r--src/mainboard/google/snow/ramstage.c5
2 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index 3e7fbb99dd..d785bebbc4 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -9,10 +9,7 @@
#include <string.h>
#include <delay.h>
#include <smbios.h>
-
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
#include "memory.c"
@@ -38,11 +35,9 @@ static void cpu_pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
-#endif
assign_resources(dev->link_list);
}
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index a3e9236ac5..5970357512 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -18,10 +18,7 @@
*/
#include <console/console.h>
-
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
void hardwaremain(int boot_complete);
void main(void)
@@ -29,13 +26,11 @@ void main(void)
console_init();
printk(BIOS_INFO, "hello from ramstage\n");
-#if CONFIG_WRITE_HIGH_TABLES
/* place at top of physical memory */
high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
high_tables_base = CONFIG_SYS_SDRAM_BASE +
((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) -
CONFIG_COREBOOT_TABLES_SIZE;
-#endif
hardwaremain(0);
}