diff options
Diffstat (limited to 'src/mainboard')
24 files changed, 11 insertions, 105 deletions
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 510b8f86f0..33ca9a2210 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -33,7 +33,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -98,7 +97,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 3c808d41cb..676ce4ef9c 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 3dc2801546..97c198895d 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 8c17b0affa..d742f50026 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -32,8 +32,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -95,7 +93,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 6cdaf42df5..a3a34d6987 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -39,8 +39,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 2172338685..2fb86f1dac 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -35,8 +35,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -112,7 +110,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 37751ce27a..03a3288358 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -17,17 +17,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 0 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 6bd7068a8a..59e21388e8 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -1,4 +1,3 @@ -#define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 1814634277..0859e370c0 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -1,4 +1,3 @@ -#define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 1983b9678f..1e4ee4c7eb 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -13,7 +13,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -63,7 +62,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { extern void RestartCAR(); - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -105,7 +104,7 @@ void cache_as_ram_main(void) We use method 1 on Norwich. */ - POST_CODE(0x02); + post_code(0x02); print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 80226a940d..f5fa9e9b0a 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -32,7 +32,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -102,7 +101,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 753488933e..4b82aa4d88 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -46,8 +46,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 67f4c3c381..efaf1dd6be 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -36,8 +36,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" @@ -132,7 +130,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 344e0eed84..51b1cf6d1d 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -37,8 +37,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" @@ -194,7 +192,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { int err; - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index ecc95d5d67..04c8dbd540 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -52,17 +52,6 @@ #include "pc80/serial.c" #include "console/console.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 0174b7b567..00e5991bf6 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -18,17 +18,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 236e530258..1ba4440324 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -33,7 +33,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ @@ -148,7 +147,7 @@ void cache_as_ram_main(void) extern void RestartCAR(); - POST_CODE(0x01); + post_code(0x01); SystemPreInit(); msr_init(); @@ -195,7 +194,7 @@ void cache_as_ram_main(void) * * We use method 1 on Norwich and on this board too. */ - POST_CODE(0x02); + post_code(0x02); print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index f3d6be0a1f..2b7ede214b 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index a16bf7ca51..71ae749ca2 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index d585edd476..4379c2457d 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -4,7 +4,6 @@ * (c) 2006 coresystems GmbH */ -#define ASM_CONSOLE_LOGLEVEL 6 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index c251e6dcec..750ca9c490 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -13,17 +13,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index bb13bb4246..eb6873c4e4 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -17,17 +17,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 0f1b09e20b..eafe326c7a 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -12,17 +12,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 5a8e94bde4..60f2d21093 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -34,7 +34,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -99,7 +98,7 @@ static void mb_gpio_init(void) void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} |