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-rw-r--r--src/mainboard/amd/dbm690t/Config.lb2
-rw-r--r--src/mainboard/amd/dbm690t/Options.lb4
-rw-r--r--src/mainboard/amd/dbm690t/devicetree.cb2
-rw-r--r--src/mainboard/amd/pistachio/Config.lb2
-rw-r--r--src/mainboard/amd/pistachio/Options.lb2
-rw-r--r--src/mainboard/amd/pistachio/devicetree.cb2
6 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
index 68255eee8c..98ff2dd0f7 100644
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ b/src/mainboard/amd/dbm690t/Config.lb
@@ -136,7 +136,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -170,7 +169,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
- register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"
diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb
index 92378ebb10..d5d54f985e 100644
--- a/src/mainboard/amd/dbm690t/Options.lb
+++ b/src/mainboard/amd/dbm690t/Options.lb
@@ -73,6 +73,7 @@ uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
+uses CONFIG_VGA_ROM_RUN
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -103,8 +104,6 @@ default CONFIG_ROM_SIZE=524288
##
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#256K
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
@@ -160,6 +159,7 @@ default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
+default CONFIG_VGA_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
index 870503789f..2e89c13aaf 100644
--- a/src/mainboard/amd/dbm690t/devicetree.cb
+++ b/src/mainboard/amd/dbm690t/devicetree.cb
@@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -33,7 +32,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
- register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb
index e0458d3609..b0f82b21c7 100644
--- a/src/mainboard/amd/pistachio/Config.lb
+++ b/src/mainboard/amd/pistachio/Config.lb
@@ -136,7 +136,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -171,7 +170,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
- register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"
diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb
index 0082151c7d..922edf5210 100644
--- a/src/mainboard/amd/pistachio/Options.lb
+++ b/src/mainboard/amd/pistachio/Options.lb
@@ -73,6 +73,7 @@ uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
+uses CONFIG_VGA_ROM_RUN
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -158,6 +159,7 @@ default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
+default CONFIG_VGA_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
index 802c000a2a..ec16256b26 100644
--- a/src/mainboard/amd/pistachio/devicetree.cb
+++ b/src/mainboard/amd/pistachio/devicetree.cb
@@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -34,7 +33,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
- register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"