diff options
Diffstat (limited to 'src/mainboard')
35 files changed, 73 insertions, 1368 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index abb2a114f8..5b062d61ff 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/mahogany_fam10/spd_addr.h b/src/mainboard/amd/mahogany_fam10/spd_addr.h deleted file mode 100644 index 489fa3330a..0000000000 --- a/src/mainboard/amd/mahogany_fam10/spd_addr.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node - RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 4 - RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 6 - RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 12 - RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 16 - RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 20 - RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 24 - RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 32 - RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 48 - RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h b/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h index c0e552a3fc..2d7ba7fc44 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -191,4 +113,3 @@ static const u8 spd_addr[] = { RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; - diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index c73a07c357..c74de742da 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/tilapia_fam10/spd_addr.h b/src/mainboard/amd/tilapia_fam10/spd_addr.h deleted file mode 100644 index 489fa3330a..0000000000 --- a/src/mainboard/amd/tilapia_fam10/spd_addr.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node - RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 4 - RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 6 - RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 12 - RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 16 - RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 20 - RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 24 - RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 32 - RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 48 - RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f6e242b8ea..f524a889d3 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/m4a785-m/spd_addr.h b/src/mainboard/asus/m4a785-m/spd_addr.h deleted file mode 100644 index 489fa3330a..0000000000 --- a/src/mainboard/asus/m4a785-m/spd_addr.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node - RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 4 - RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 6 - RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 12 - RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 16 - RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 20 - RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 24 - RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 32 - RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 48 - RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index fea599b2a6..0d8746bcfc 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -75,7 +75,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c index 45315618b7..7904c0635a 100644 --- a/src/mainboard/dell/s1850/debug.c +++ b/src/mainboard/dell/s1850/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -208,8 +206,8 @@ static void dump_pci_devices(void) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -233,7 +231,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -241,8 +239,8 @@ void dump_spd_registers(void) void show_dram_slots(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -257,7 +255,7 @@ void show_dram_slots(void) } print_debug_hex8(status); print_debug("\n"); - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -285,7 +283,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 3286e028f4..ec3fbcd302 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -82,10 +82,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a61be0a9ab..dcd523f057 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -86,10 +86,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/dl165_g6_fam10/spd_addr.h b/src/mainboard/hp/dl165_g6_fam10/spd_addr.h index 6a201c7e61..4576499ebc 100644 --- a/src/mainboard/hp/dl165_g6_fam10/spd_addr.h +++ b/src/mainboard/hp/dl165_g6_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr @@ -108,4 +30,3 @@ static const u8 spd_addr[] = { RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; - diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e92f29d26c..de213534f8 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -89,11 +89,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/iei/kino-780am2-fam10/spd_addr.h b/src/mainboard/iei/kino-780am2-fam10/spd_addr.h deleted file mode 100644 index 489fa3330a..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/spd_addr.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node - RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 4 - RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 6 - RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 12 - RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 16 - RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 20 - RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 24 - RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 32 - RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 48 - RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index f98ca8e9b8..e5795b6532 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -20,9 +20,7 @@ * MA 02110-1301 USA */ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -230,8 +228,8 @@ static inline void dump_pci_devices(void) static inline void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -254,7 +252,7 @@ static inline void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -281,7 +279,7 @@ static inline void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index 1fa2f0857b..0d70b70f82 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -81,7 +81,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 6944fcc302..0ba51b14a1 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -94,9 +94,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/msi/ms9652_fam10/spd_addr.h b/src/mainboard/msi/ms9652_fam10/spd_addr.h index a8abf331ee..40c5ac712a 100644 --- a/src/mainboard/msi/ms9652_fam10/spd_addr.h +++ b/src/mainboard/msi/ms9652_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ static const u8 spd_addr[] = { RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 4b7d0fde04..5ccc348047 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -89,7 +89,7 @@ static u8 spd_read_byte(u8 device, u8 address) print_debug("spd_read_byte dev "); print_debug_hex8(device); - if (device != (0x50 << 1)) { + if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } @@ -123,7 +123,7 @@ static void mb_gpio_init(void) void main(unsigned long bist) { static const struct mem_controller memctrl[] = { - {.channel0 = {0x50}}, + {.channel0 = {DIMM0}}, }; post_code(0x01); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 44e14ac7ec..0312d4a27c 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -88,7 +88,7 @@ static u8 spd_read_byte(u8 device, u8 address) print_debug("spd_read_byte dev "); print_debug_hex8(device); - if (device != (0x50 << 1)) { + if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } @@ -144,7 +144,7 @@ static void mb_gpio_init(void) void main(unsigned long bist) { static const struct mem_controller memctrl[] = { - {.channel0 = {0x50}}, + {.channel0 = {DIMM0}}, }; post_code(0x01); diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index c838da1f1a..eec73a1942 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -45,15 +45,16 @@ /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the * values have to be set manually, the SO-DIMM socket is located in - * socket0 (0x50), and the onboard memory is located in socket1 (0x51). + * socket0 (0x50/DIMM0), and the onboard memory is located in socket1 + * (0x51/DIMM1). */ static inline int spd_read_byte(unsigned device, unsigned address) { int i; - if (device == 0x50) { + if (device == DIMM0) { return smbus_read_byte(device, address); - } else if (device == 0x51) { + } else if (device == DIMM1) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) return spd_table[i].data; diff --git a/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h b/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h index a8abf331ee..40c5ac712a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h +++ b/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ static const u8 spd_addr[] = { RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - diff --git a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h index 5b32b4c2d6..1bcf039198 100644 --- a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h +++ b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -113,4 +35,3 @@ static const u8 spd_addr[] = { RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, #endif }; - diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index 87c67b5964..93199d7b8a 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ void dump_spd_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ void dump_ipmi_registers(void) print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 515059ac09..e6f91848cd 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -46,15 +46,16 @@ /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the * values have to be set manually, the SO-DIMM socket is located in - * socket0 (0x50), and the onboard memory is located in socket1 (0x51). + * socket0 (0x50/DIMM0), and the onboard memory is located in socket1 + * (0x51/DIMM1). */ static inline int spd_read_byte(unsigned device, unsigned address) { int i; - if (device == 0x50) { + if (device == DIMM0) { return smbus_read_byte(device, address); - } else if (device == 0x51) { + } else if (device == DIMM1) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) return spd_table[i].data; diff --git a/src/mainboard/tyan/s2912_fam10/spd_addr.h b/src/mainboard/tyan/s2912_fam10/spd_addr.h index a8abf331ee..40c5ac712a 100644 --- a/src/mainboard/tyan/s2912_fam10/spd_addr.h +++ b/src/mainboard/tyan/s2912_fam10/spd_addr.h @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ static const u8 spd_addr[] = { RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 06562176d0..45df349cbc 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -75,7 +75,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 4526ddcde8..1b4e27a7af 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -50,7 +50,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; static inline int spd_read_byte(unsigned device, unsigned address) diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 5f4c67b33d..0b5a557125 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -51,7 +51,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */ + .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; void main(unsigned long bist) diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index e7361b7f73..8c761464f2 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -91,7 +91,7 @@ void main(unsigned long bist) /* Set statically so it should work with cx700 as well */ static const struct mem_controller cx700[] = { { - .channel0 = {0x50, 0x51}, + .channel0 = {DIMM0, DIMM1}, }, }; |