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-rw-r--r--src/mainboard/google/hatch/romstage.c54
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h7
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h3
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/memory.c33
-rw-r--r--src/mainboard/google/hatch/variants/kohaku/memory.c29
-rw-r--r--src/mainboard/google/sarien/romstage.c27
-rw-r--r--src/mainboard/intel/coffeelake_rvp/memory.c25
-rw-r--r--src/mainboard/intel/coffeelake_rvp/romstage.c10
8 files changed, 94 insertions, 94 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index bdf951b016..2c630a8ce8 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -16,23 +16,63 @@
#include <baseboard/variants.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
#include <memory_info.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <string.h>
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_F20
+#define GPIO_MEM_CONFIG_1 GPP_F21
+#define GPIO_MEM_CONFIG_2 GPP_F11
+#define GPIO_MEM_CONFIG_3 GPP_F22
+
+/*
+ * GPIO_MEM_CH_SEL is set to 1 for single channel skus
+ * and 0 for dual channel skus.
+ */
+#define GPIO_MEM_CH_SEL GPP_F2
+
+static int memory_sku(void)
+{
+ const gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
struct cnl_mb_cfg memcfg;
-
- const struct spd_info spd = {
- .spd_by_index = true,
- .spd_spec.spd_index = variant_memory_sku(),
- };
+ int mem_sku;
+ int is_single_ch_mem;
variant_memory_params(&memcfg);
- cannonlake_memcfg_init(&memupd->FspmConfig,
- &memcfg, &spd);
+ mem_sku = memory_sku();
+ /*
+ * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
+ * channel skus and 0 for dual channel skus.
+ */
+ is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL);
+
+ /*
+ * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively.
+ * Dual-DIMM memory is not used in hatch family, so we only
+ * fill in spd_info for CH0D0 and CH1D0 here.
+ */
+ memcfg.spd[0].read_type = READ_SPD_CBFS;
+ memcfg.spd[0].spd_spec.spd_index = mem_sku;
+ if (!is_single_ch_mem) {
+ memcfg.spd[2].read_type = READ_SPD_CBFS;
+ memcfg.spd[2].spd_spec.spd_index = mem_sku;
+ }
+
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}
void mainboard_get_dram_part_num(const char **part_num, size_t *len)
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index 5d6311ba24..e83732cb62 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -22,13 +22,6 @@
#define GPIO_PCH_WP GPP_C20
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0 GPP_F20
-#define GPIO_MEM_CONFIG_1 GPP_F21
-#define GPIO_MEM_CONFIG_2 GPP_F11
-#define GPIO_MEM_CONFIG_3 GPP_F22
-
-
/* EC wake pin is LAN_WAKE# */
#define GPE_EC_WAKE GPE0_LAN_WAK
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index d41ad536f2..17bd5df63d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -31,9 +31,6 @@ const struct pad_config *base_early_gpio_table(size_t *num);
const struct pad_config *override_gpio_table(size_t *num);
const struct pad_config *override_early_gpio_table(size_t *num);
-/* Return memory SKU for the board. */
-int variant_memory_sku(void);
-
/* Return board specific memory configuration */
void variant_memory_params(struct cnl_mb_cfg *bcfg);
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
index 580bdc9ab3..bcfc49f20e 100644
--- a/src/mainboard/google/hatch/variants/baseboard/memory.c
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -15,16 +15,15 @@
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
-#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <string.h>
static const struct cnl_mb_cfg baseboard_memcfg = {
/* Baseboard uses 121, 81 and 100 rcomp resistors */
- .rcomp_resistor = { 121, 81, 100 },
+ .rcomp_resistor = {121, 81, 100},
/* Baseboard Rcomp target values */
- .rcomp_targets = { 100, 40, 20, 20, 26 },
+ .rcomp_targets = {100, 40, 20, 20, 26},
/* Set CaVref config to 2 */
.vref_ca_config = 2,
@@ -36,32 +35,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
{
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
- /*
- * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
- * channel skus and 0 for dual channel skus.
- */
- if (gpio_get(GPP_F2) == 1) {
- /*
- * Single channel config: for Hatch, Channel 0 is
- * always populated.
- */
- bcfg->channel_empty[0] = 0;
- bcfg->channel_empty[1] = 1;
- } else {
- /* Dual channel config: both channels populated. */
- bcfg->channel_empty[0] = 0;
- bcfg->channel_empty[1] = 0;
- }
-}
-
-int __weak variant_memory_sku(void)
-{
- const gpio_t spd_gpios[] = {
- GPIO_MEM_CONFIG_0,
- GPIO_MEM_CONFIG_1,
- GPIO_MEM_CONFIG_2,
- GPIO_MEM_CONFIG_3,
- };
-
- return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c
index 27ae3d8fb2..490124776e 100644
--- a/src/mainboard/google/hatch/variants/kohaku/memory.c
+++ b/src/mainboard/google/hatch/variants/kohaku/memory.c
@@ -15,7 +15,6 @@
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
-#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <string.h>
@@ -30,8 +29,8 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
* the index = pin number on SoC
* the value = pin number on lpddr3 part
*/
- .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 5, 7, 6, 4 },
- .dqs_map[DDR_CH1] = { 1, 3, 2, 0, 5, 7, 6, 4 },
+ .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4},
+ .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4},
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
@@ -40,7 +39,7 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
- },
+ },
.dq_map[DDR_CH1] = {
{0xf, 0xf0},
{0x0, 0xf0},
@@ -48,13 +47,13 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
- },
+ },
/* Kohaku uses 200, 80.6 and 162 rcomp resistors */
- .rcomp_resistor = { 200, 81, 162 },
+ .rcomp_resistor = {200, 81, 162},
/* Kohaku Rcomp target values */
- .rcomp_targets = { 100, 40, 40, 23, 40 },
+ .rcomp_targets = {100, 40, 40, 23, 40},
/* Set CaVref config to 0 for LPDDR3 */
.vref_ca_config = 0,
@@ -66,20 +65,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
void variant_memory_params(struct cnl_mb_cfg *bcfg)
{
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
- /*
- * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
- * channel skus and 0 for dual channel skus.
- */
- if (gpio_get(GPP_F2) == 1) {
- /*
- * Single channel config: for kohaku, Channel 0 is
- * always populated.
- */
- bcfg->channel_empty[0] = 0;
- bcfg->channel_empty[1] = 1;
- } else {
- /* Dual channel config: both channels populated. */
- bcfg->channel_empty[0] = 0;
- bcfg->channel_empty[1] = 0;
- }
}
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index e83cd4aed4..20eee7f34b 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -18,6 +18,18 @@
#include <soc/romstage.h>
static const struct cnl_mb_cfg memcfg = {
+ /* Access memory info through SMBUS. */
+ .spd[0] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa0},
+ },
+ .spd[1] = {.read_type = NOT_EXISTING},
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa4},
+ },
+ .spd[3] = {.read_type = NOT_EXISTING},
+
/*
* The dqs_map arrays map the ddr4 pins to the SoC pins
* for both channels.
@@ -25,16 +37,16 @@ static const struct cnl_mb_cfg memcfg = {
* the index = pin number on ddr4 part
* the value = pin number on SoC
*/
- .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
- .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+ .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
+ .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
/* Baseboard uses 121, 81 and 100 rcomp resistors */
- .rcomp_resistor = { 121, 81, 100 },
+ .rcomp_resistor = {121, 81, 100},
/*
* Baseboard Rcomp target values.
*/
- .rcomp_targets = { 100, 40, 20, 20, 26 },
+ .rcomp_targets = {100, 40, 20, 20, 26},
/* Disable Early Command Training */
.ect = 0,
@@ -45,12 +57,7 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- const struct spd_info spd = {
- .spd_smbus_address[0] = 0xa0,
- .spd_smbus_address[2] = 0xa4
- };
-
wilco_ec_romstage_init();
- cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd);
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}
diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c
index a13000cc13..b093a20d2c 100644
--- a/src/mainboard/intel/coffeelake_rvp/memory.c
+++ b/src/mainboard/intel/coffeelake_rvp/memory.c
@@ -20,6 +20,23 @@
#include <soc/cnl_memcfg_init.h>
static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
+ /* Access memory info through SMBUS. */
+ .spd[0] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xA0}
+ },
+ .spd[1] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xA2}
+ },
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xA4}
+ },
+ .spd[3] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xA6}
+ },
/*
* The dqs_map arrays map the ddr4 pins to the SoC pins
* for both channels.
@@ -27,16 +44,16 @@ static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
* the index = pin number on ddr4 part
* the value = pin number on SoC
*/
- .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 },
- .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 },
+ .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7},
+ .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7},
/* Baseboard uses 121, 81 and 100 rcomp resistors */
- .rcomp_resistor = { 121, 81, 100 },
+ .rcomp_resistor = {121, 81, 100},
/*
* Baseboard Rcomp target values.
*/
- .rcomp_targets = { 100, 40, 20, 20, 26 },
+ .rcomp_targets = {100, 40, 20, 20, 26},
/* Baseboard is an interleaved design */
.dq_pins_interleaved = 1,
diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c
index 1ab2d78b5a..09ef148e36 100644
--- a/src/mainboard/intel/coffeelake_rvp/romstage.c
+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c
@@ -20,13 +20,5 @@
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- const struct spd_info spd = {
- .spd_smbus_address[0] = 0xA0,
- .spd_smbus_address[1] = 0xA2,
- .spd_smbus_address[2] = 0xA4,
- .spd_smbus_address[3] = 0xA6,
- };
-
- cannonlake_memcfg_init(&memupd->FspmConfig,
- variant_memcfg_config(), &spd);
+ cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config());
}