diff options
Diffstat (limited to 'src/mainboard')
177 files changed, 18906 insertions, 958 deletions
diff --git a/src/mainboard/Iwill/DK8S2/Config.lb b/src/mainboard/Iwill/DK8S2/Config.lb index 661cadcdd2..22c589f6c0 100644 --- a/src/mainboard/Iwill/DK8S2/Config.lb +++ b/src/mainboard/Iwill/DK8S2/Config.lb @@ -45,6 +45,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o ## ATI Rage XL framebuffering graphics driver dir /drivers/ati/ragexl @@ -129,7 +130,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -# config for arima/hdama +# config for Iwill/DK8S2 chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 @@ -189,7 +190,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end end @@ -208,7 +209,7 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end diff --git a/src/mainboard/Iwill/DK8S2/Options.lb b/src/mainboard/Iwill/DK8S2/Options.lb index d7b694d1f8..5cb440f504 100644 --- a/src/mainboard/Iwill/DK8S2/Options.lb +++ b/src/mainboard/Iwill/DK8S2/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -76,13 +73,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/Iwill/DK8S2/reset.c b/src/mainboard/Iwill/DK8S2/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/Iwill/DK8S2/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb index d8fc0cb5e0..59f3828239 100644 --- a/src/mainboard/Iwill/DK8X/Config.lb +++ b/src/mainboard/Iwill/DK8X/Config.lb @@ -45,6 +45,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o ## ## Romcc output diff --git a/src/mainboard/Iwill/DK8X/Options.lb b/src/mainboard/Iwill/DK8X/Options.lb index 0f413f0499..6265e72fe1 100644 --- a/src/mainboard/Iwill/DK8X/Options.lb +++ b/src/mainboard/Iwill/DK8X/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -76,13 +73,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/Iwill/DK8X/reset.c b/src/mainboard/Iwill/DK8X/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/Iwill/DK8X/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb index 2d818d40d1..5adaf354d7 100644 --- a/src/mainboard/amd/quartet/Config.lb +++ b/src/mainboard/amd/quartet/Config.lb @@ -41,6 +41,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o ## ## Romcc output diff --git a/src/mainboard/amd/quartet/Options.lb b/src/mainboard/amd/quartet/Options.lb index 7e2dc489ae..f1013eaadf 100644 --- a/src/mainboard/amd/quartet/Options.lb +++ b/src/mainboard/amd/quartet/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -75,13 +72,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/amd/quartet/reset.c b/src/mainboard/amd/quartet/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/amd/quartet/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/amd/serenade/Config.lb b/src/mainboard/amd/serenade/Config.lb index 4fdc235507..deac98b563 100644 --- a/src/mainboard/amd/serenade/Config.lb +++ b/src/mainboard/amd/serenade/Config.lb @@ -41,6 +41,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o ## ## Romcc output diff --git a/src/mainboard/amd/serenade/Options.lb b/src/mainboard/amd/serenade/Options.lb index fedc518d8a..a26f2709f8 100644 --- a/src/mainboard/amd/serenade/Options.lb +++ b/src/mainboard/amd/serenade/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -74,13 +71,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/amd/serenade/reset.c b/src/mainboard/amd/serenade/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/amd/serenade/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb index fdf3c1c769..6feb8b1848 100644 --- a/src/mainboard/amd/solo/Config.lb +++ b/src/mainboard/amd/solo/Config.lb @@ -42,6 +42,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_ACPI_TABLES object acpi_tables.o end +object reset.o ## ## Romcc output diff --git a/src/mainboard/amd/solo/Options.lb b/src/mainboard/amd/solo/Options.lb index 42611440f6..87a2ceb4bc 100644 --- a/src/mainboard/amd/solo/Options.lb +++ b/src/mainboard/amd/solo/Options.lb @@ -4,9 +4,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -76,13 +73,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/amd/solo/reset.c b/src/mainboard/amd/solo/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/amd/solo/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index a9df17bcdf..0b04d51214 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -29,7 +29,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## -default XIP_ROM_SIZE=65536 +default XIP_ROM_SIZE=131072 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) ## @@ -45,13 +45,13 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" + depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end @@ -60,11 +60,11 @@ makerule ./failover.inc action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end -makerule ./auto.inc +makerule ./auto.inc depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end @@ -129,61 +129,122 @@ config chip.h # config for arima/hdama chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on end # PCIX bridge + device pci 0.0 on # PCIX bridge + ## On board NIC A + #chip drivers/generic/generic + # device pci 3.0 on + # irq 0 = 0x13 + # end + #end + ## On board NIC B + #chip drivers/generic/generic + # device pci 4.0 on + # irq 0 = 0x13 + # end + #end + ## PCI Slot 3 + #chip drivers/generic/generic + # device pci 1.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 4 + #chip drivers/generic/generic + # device pci 2.0 on + # irq 0 = 0x12 + # irq 1 = 0x13 + # irq 2 = 0x10 + # irq 3 = 0x11 + # end + #end + end device pci 0.1 on end # IOAPIC - device pci 1.0 on end # PCIX bridge - device pci 1.1 on end # IOAPIC + device pci 1.0 on # PCIX bridge + ## PCI Slot 1 + #chip drivers/generic/generic + # device pci 1.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 2 + #chip drivers/generic/generic + # device pci 2.0 on + # irq 0 = 0x12 + # irq 1 = 0x13 + # irq 2 = 0x10 + # irq 3 = 0x11 + # end + #end + end + device pci 1.1 on end # IOAPIC end chip southbridge/amd/amd8111 # this "device pci 0.0" is the parent of the next one # PCI bridge device pci 0.0 on - device pci 0.0 on end # USB0 - device pci 0.1 on end # USB1 - device pci 0.2 off end # USB 2.0 - device pci 1.0 off end # LAN + device pci 0.0 on end # USB0 + device pci 0.1 on end # USB1 + device pci 0.2 off end # USB 2.0 + device pci 1.0 off end # LAN chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL register "rom_address" = "0xfff80000" end + ## PCI Slot 5 (correct?) + #chip drivers/generic/generic + # device pci 5.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 6 (correct?) + #chip drivers/generic/generic + # device pci 4.0 on + # irq 0 = 0x10 + # irq 1 = 0x11 + # irq 2 = 0x12 + # irq 3 = 0x13 + # end + #end + end # LPC bridge device pci 1.0 on chip superio/NSC/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.4 off end # SWC device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.6 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -239,7 +300,7 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT1 device pci 18.0 on end # LDT2 @@ -255,6 +316,14 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end end end diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb index 773d698ad2..9d70f5b7ef 100644 --- a/src/mainboard/arima/hdama/Options.lb +++ b/src/mainboard/arima/hdama/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -80,13 +77,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c index b4d955385f..7790b3ea50 100644 --- a/src/mainboard/arima/hdama/auto.c +++ b/src/mainboard/arima/hdama/auto.c @@ -11,6 +11,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#include "northbridge/amd/amdk8/cpu_rev.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -18,28 +19,59 @@ #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/NSC/pc87360/pc87360_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { - set_bios_reset(); + device_t dev; + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + set_bios_reset(); outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + /* Reset */ set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } /* @@ -128,6 +160,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" +#include "debug.c" #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -160,13 +193,14 @@ static void main(unsigned long bist) }; int needs_reset; - unsigned nodeid; if (bist == 0) { + unsigned nodeid; /* Skip this if there was a built in self test failure */ amd_early_mtrr_init(); enable_lapic(); init_timer(); nodeid = lapicid() & 0xf; + /* Has this cpu already booted? */ if (cpu_init_detected(nodeid)) { asm volatile ("jmp __cpu_reset"); @@ -191,13 +225,12 @@ static void main(unsigned long bist) print_info("ht reset -\r\n"); soft_reset(); } - #if 0 print_pci_devices(); #endif enable_smbus(); #if 0 - dump_spd_registers(&cpu[0]); + dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu); #endif memreset_setup(); @@ -205,6 +238,8 @@ static void main(unsigned long bist) #if 0 dump_pci_devices(); +#endif +#if 0 dump_pci_device(PCI_DEV(0, 0x18, 2)); #endif diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c new file mode 100644 index 0000000000..55c62649c8 --- /dev/null +++ b/src/mainboard/arima/hdama/debug.c @@ -0,0 +1,143 @@ + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +static void dump_spd_registers(int controllers, const struct mem_controller *ctrl) +{ + int n; + for(n = 0; n < controllers; n++) { + int i; + print_debug("\r\n"); + activate_spd_rom(&ctrl[n]); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl[n].channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(n); + print_debug_char('.'); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = spd_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } +#if 0 + byte = status & 0xff; + print_debug_hex8(byte); +#else + print_debug_hex8(status & 0xff); +#endif + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl[n].channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(n); + print_debug_char('.'); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = spd_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } +#if 0 + byte = status & 0xff; + print_debug_hex8(byte); +#else + print_debug_hex8(status & 0xff); +#endif + print_debug_char(' '); + } + print_debug("\r\n"); + } + } + } +} diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 9287b7333e..ef32251e7d 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -4,6 +4,40 @@ #include <string.h> #include <stdint.h> +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -12,6 +46,7 @@ void *smp_write_config_table(void *v) struct mp_config_table *mc; unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -38,8 +73,15 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -52,7 +94,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -63,7 +105,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -87,7 +129,7 @@ void *smp_write_config_table(void *v) device_t dev; struct resource *res; /* 8131 apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -95,7 +137,7 @@ void *smp_write_config_table(void *v) } } /* 8131 apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { diff --git a/src/mainboard/arima/hdama/reset.c b/src/mainboard/arima/hdama/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/arima/hdama/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/emulation/qemu-i386/Options.lb b/src/mainboard/emulation/qemu-i386/Options.lb index 9047dc6000..d12a1c3592 100644 --- a/src/mainboard/emulation/qemu-i386/Options.lb +++ b/src/mainboard/emulation/qemu-i386/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -73,13 +70,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=0 ## -## Funky hard reset implementation -## -# default HARD_RESET_BUS=1 -# default HARD_RESET_DEVICE=4 -# default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=0 diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb index 604a82d46d..1633c8f810 100644 --- a/src/mainboard/ibm/e325/Config.lb +++ b/src/mainboard/ibm/e325/Config.lb @@ -45,6 +45,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o ## ## Romcc output diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb index 9bad595658..a1b21fd68a 100644 --- a/src/mainboard/ibm/e325/Options.lb +++ b/src/mainboard/ibm/e325/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -75,13 +72,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/ibm/e325/reset.c b/src/mainboard/ibm/e325/reset.c new file mode 100644 index 0000000000..7f58d01410 --- /dev/null +++ b/src/mainboard/ibm/e325/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 1); +} diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb new file mode 100644 index 0000000000..adca342a78 --- /dev/null +++ b/src/mainboard/intel/jarrell/Config.lb @@ -0,0 +1,213 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 + device pci_domain 0 on + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + device pci 00.0 on end + device pci 00.1 on end + device pci 00.2 on + chip drivers/generic/generic + device pci 04.0 on end + device pci 04.1 on end + end + end + device pci 00.3 on end + end + end + device pci 06.0 on end + chip southbridge/intel/ich5r # ich5r + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 off end + device pci 1d.7 on end + device pci 1e.0 on + chip drivers/ati/ragexl + device pci 0c.0 on end + end + end + device pci 1f.0 on + chip superio/NSC/pc87427 + device pnp 2e.0 off end + device pnp 2e.2 on +# io 0x60 = 0x2f8 +# irq 0x70 = 3 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on +# io 0x60 = 0x3f8 +# irq 0x70 = 4 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a off end + device pnp 2e.f on end + device pnp 2e.10 off end + device pnp 2e.14 off end + end + end + device pci 1f.1 on end + device pci 1f.2 off end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" + register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW" + register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" + end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + device apic 6 on end + end + end +end diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb new file mode 100644 index 0000000000..a7a5c7288a --- /dev/null +++ b/src/mainboard/intel/jarrell/Options.lb @@ -0,0 +1,242 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY +uses MAX_REBOOT_CNT +uses USE_WATCHDOG_ON_BOOT + + +### +### Build options +### + +## +## Because we do the stutter start we need more attempts +## +default MAX_REBOOT_CNT=8 + +## +## Use the watchdog to break out of a lockup condition +## +default USE_WATCHDOG_ON_BOOT=1 + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=2097152 + + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=9 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="SE7520JR22D" +default MAINBOARD_VENDOR= "Intel" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 +#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c new file mode 100644 index 0000000000..7e9cd99e96 --- /dev/null +++ b/src/mainboard/intel/jarrell/auto.c @@ -0,0 +1,150 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/ich5r/ich5r_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/NSC/pc87427/pc87427.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "watchdog.c" +#include "reset.c" +#include "power_reset_check.c" +#include "jarrell_fixups.c" +#include "superio/NSC/pc87427/pc87427_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +/* Beta values: 0x00090800 */ +/* Silver values: 0x000a0900 */ +#define RECVENA_CONFIG 0x000a090a +#define RECVENB_CONFIG 0x000a090a +#define DIMM_MAP_LOGICAL 0x0124 + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" +#include "debug.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 }, + .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + pc87427_disable_dev(CONSOLE_SERIAL_DEV); + pc87427_disable_dev(HIDDEN_SERIAL_DEV); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + /* Enable Serial 2 lines instead of GPIO */ + outb(0x2c, 0x2e); + outb((inb(0x2f) & (~1<<1)), 0x2f); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE); + + pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE); + xbus_cfg(PC87427_XBUS_DEV); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + print_pci_devices(); +#endif + enable_smbus(); +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); + power_down_reset_check(); +// dump_ipmi_registers(); + mainboard_set_e7520_leds(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + ich5_watchdog_on(); +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, 0x01000000); + /* check the first 1M in the 3rd Gig */ + ram_check(0x30100000, 0x31000000); +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#endif +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/intel/jarrell/chip.h b/src/mainboard/intel/jarrell/chip.h new file mode 100644 index 0000000000..7cc59091bd --- /dev/null +++ b/src/mainboard/intel/jarrell/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_intel_jarrell_ops; + +struct mainboard_intel_jarrell_config { + int nothing; +}; diff --git a/src/mainboard/intel/jarrell/cmos.layout b/src/mainboard/intel/jarrell/cmos.layout new file mode 100644 index 0000000000..71387a2e4b --- /dev/null +++ b/src/mainboard/intel/jarrell/cmos.layout @@ -0,0 +1,82 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 376 r 0 reserved_memory +376 1 e 1 power_up_watchdog +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +397 1 e 1 pxhd_bus_speed_100 +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/intel/jarrell/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/intel/jarrell/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/intel/jarrell/irq_tables.c b/src/mainboard/intel/jarrell/irq_tables.c new file mode 100644 index 0000000000..75071c131a --- /dev/null +++ b/src/mainboard/intel/jarrell/irq_tables.c @@ -0,0 +1,37 @@ +/* PCI: Interrupt Routing Table found at 0x40114180 size = 320 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 320, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x24d0, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x38, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, 0xe8, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x02, 0x20, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x03, 0x28, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, 0x60, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x02, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x04, 0x00}, + {0x02, 0x10, {{0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x05, 0x00}, + {0x02, 0x18, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}}, 0x06, 0x00}, + {0x03, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x01, 0x00}, + {0x03, 0x10, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}}, 0x02, 0x00}, + {0x03, 0x18, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x03, 0x00}, + {0x00, 0x10, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}, + {0x00, 0x18, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}, + {0x00, 0x20, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}, + {0x00, 0x28, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}, + {0x00, 0x30, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}, + {0x00, 0x38, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00} + } +}; diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c new file mode 100644 index 0000000000..d8c694b4af --- /dev/null +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -0,0 +1,123 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev != PCI_DEV_INVALID) { + /* I/O space is always enables */ + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); + base = ICH5_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Set GPIO 19 mux to IO usage */ + value = inl(base); + value |= (1 <<19); + outl(value, base); + + /* Pull GPIO 19 low */ + value = inl(base + 0x0c); + value &= ~(1 << 19); + outl(value, base + 0x0c); + } + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + uint16_t gpio_index; + uint8_t data; + device_t dev; + + /* currently only handle the Jarrell/PC87427 case */ + dev = PC87427_GPIO_DEV; + + + pnp_set_logical_device(dev); + gpio_index = pnp_read_iobase(dev, 0x60); + + /* select SIO GPIO port 4, pin 2 */ + pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42)); + /* set to push-pull, enable output */ + pnp_write_config(dev, PC87427_GPCFG1, 0x03); + + /* select SIO GPIO port 4, pin 4 */ + pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44)); + /* set to push-pull, enable output */ + pnp_write_config(dev, PC87427_GPCFG1, 0x03); + + /* set gpio 42,44 signal levels */ + data = inb(gpio_index + PC87427_GPDO_4); + if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) { + print_debug("set_pllsel: correct settings detected!\r\n"); + return; /* settings already configured */ + } else { + outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4); + /* reset */ + print_debug("set_pllsel: settings adjusted, now resetting...\r\n"); + // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ +// mch_reset(); + full_reset(); + } + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + uint8_t cnt; + uint8_t data; + device_t dev; + + /* currently only handle the Jarrell/PC87427 case */ + dev = PC87427_GPIO_DEV; + + pnp_set_logical_device(dev); + + /* enable */ + outb(0x30, 0x2e); + outb(0x01, 0x2f); + outb(0x2d, 0x2e); + outb(0x01, 0x2f); + + /* Set auto mode for dimm leds and post */ + outb(0xf0,0x2e); + outb(0x70,0x2f); + outb(0xf4,0x2e); + outb(0x30,0x2f); + outb(0xf5,0x2e); + outb(0x88,0x2f); + outb(0xf6,0x2e); + outb(0x00,0x2f); + outb(0xf7,0x2e); + outb(0x90,0x2f); + outb(0xf8,0x2e); + outb(0x00,0x2f); + + /* Turn the leds off */ + outb(0x00,0x88); + outb(0x00,0x90); + + /* Disable the ports */ + outb(0xf5,0x2e); + outb(0x00,0x2f); + outb(0xf7,0x2e); + outb(0x00,0x2f); + outb(0xf4,0x2e); + outb(0x00,0x2f); + + return; +} + + + + diff --git a/src/mainboard/intel/jarrell/mainboard.c b/src/mainboard/intel/jarrell/mainboard.c new file mode 100644 index 0000000000..9b25e0adeb --- /dev/null +++ b/src/mainboard/intel/jarrell/mainboard.c @@ -0,0 +1,13 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_intel_e7520_ops = { + CHIP_NAME("Intel Jarell mainboard ") +}; + diff --git a/src/mainboard/intel/jarrell/microcode_updates.c b/src/mainboard/intel/jarrell/microcode_updates.c new file mode 100644 index 0000000000..54daab0779 --- /dev/null +++ b/src/mainboard/intel/jarrell/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = { + /* + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + These microcode updates are distributed for the sole purpose of + installation in the BIOS or Operating System of computer systems + which include an Intel P6 family microprocessor sold or distributed + to or by you. You are authorized to copy and install this material + on such systems. You are not authorized to use this material for + any other purpose. + */ + + /* M1DF340E.TXT - Noconoa D-0 */ + + + 0x00000001, /* Header Version */ + 0x0000000e, /* Patch ID */ + 0x05042004, /* DATE */ + 0x00000f34, /* CPUID */ + 0x9b18561d, /* Checksum */ + 0x00000001, /* Loader Version */ + 0x0000001d, /* Platform ID */ + 0x000017d0, /* Data size */ + 0x00001800, /* Total size */ + 0x00000000, /* reserved */ + 0x00000000, /* reserved */ + 0x00000000, /* reserved */ + 0x9fbf327a, + 0x2b41b451, + 0xb0a79cab, + 0x6b62b8fd, + 0xc953d679, + 0x1e462145, + 0x59d96ae5, + 0xb90dfc00, + 0x4f6bd233, + 0xa8dda234, + 0xb96b5eb7, + 0x588fc98f, + 0xdd59a87c, + 0xb038ad4c, + 0x338af84c, + 0x44842e0d, + 0x2e664aa6, + 0xd46497b7, + 0xddbcd376, + 0xd86dd62a, + 0x27ceec6e, + 0xb089ff2e, + 0xfc549965, + 0x556f5b78, + 0xa8c4732c, + 0x0969180d, + 0x14a346e8, + 0x561a91b3, + 0x1cd21cde, + 0xd09d06bc, + 0x3a4cae91, + 0x5d23fa54, + 0x43747e8d, + 0x19ff0547, + 0xdae0e17a, + 0xc16bab85, + 0x2364fea6, + 0x8508f3c6, + 0x598ca70f, + 0x72fb0579, + 0x24c28f46, + 0xed19ad6b, + 0xcd6206fe, + 0xe3d091e8, + 0xb7f1f9f1, + 0x501c1c77, + 0x5fdda272, + 0xbdc8301b, + 0x64b200ea, + 0xb8460b09, + 0x26d125ea, + 0x03e27414, + 0x3d023f17, + 0x0b0520c8, + 0x74fba5c6, + 0xc3d761de, + 0x672cf9fa, + 0x4c000ff0, + 0x0a8bbda4, + 0x5dd7b3b1, + 0x439e12f1, + 0x235444bb, + 0xa7513c27, + 0x8ce97fbf, + 0xb41f857c, + 0x6e71fd9d, + 0xd11f2fe3, + 0x5d92f44d, + 0x4b06f5fa, + 0x7695eed0, + 0x3aa045e8, + 0x9ce894d4, + 0x02a1723a, + 0xa4d9e99e, + 0x0ca6f5ec, + 0x1df8ee10, + 0x82d9b0a9, + 0xb7fceca0, + 0x0eebfe97, + 0xda2e8c7b, + 0xf9ffdf4b, + 0xb6c84538, + 0xb7eee9d7, + 0x89f8e993, + 0x7d51dbf8, + 0xc75f6389, + 0xd2e76e6c, + 0x60fdc275, + 0x6758a029, + 0x9d463f02, + 0x40069261, + 0x55ebc0b5, + 0xa90d5bb2, + 0x33a3d807, + 0xa6e603c8, + 0x4b0e2505, + 0xd28eb45d, + 0xeab8055b, + 0x97439c5f, + 0xb3ccb9dd, + 0xb33f1bb5, + 0xd34e6009, + 0x946e7d07, + 0x68908cea, + 0x435581e5, + 0xb2ceee79, + 0x112df532, + 0xd7d079f5, + 0xbcb997f9, + 0xdc3c7807, + 0x5c6b4af9, + 0x3f919e49, + 0x62a597b9, + 0x20e4fc37, + 0x4241bc5c, + 0x66636de1, + 0x2a0f3988, + 0x62281e5f, + 0x9d19500a, + 0x9f349dbf, + 0x9b16869d, + 0x0299fec1, + 0xa013cf08, + 0x36e47a83, + 0x8cf78105, + 0xa92a7080, + 0xece3a363, + 0x01361d90, + 0x1555e2b4, + 0x9ec1207c, + 0x93f5f638, + 0x1854d4e4, + 0xa5768108, + 0xe6b867bc, + 0xec91c0a3, + 0xb42c40b9, + 0x7a543ed2, + 0xbe080c40, + 0x72edfcda, + 0xd2ddde37, + 0x1e1f1563, + 0xd24ca500, + 0x761df139, + 0xc9e79091, + 0xab44cdcb, + 0x16c204d7, + 0x5d4ff67b, + 0x8651ea63, + 0x09d8dc41, + 0x643cddcf, + 0x5709c4b7, + 0x04384755, + 0x30e52749, + 0x1329aac2, + 0x7bf64fad, + 0x5d3e6b49, + 0x515aa075, + 0xfe7e7f8d, + 0x5461d781, + 0x0547b8b2, + 0xa71b89c7, + 0x30f03604, + 0xe37970a5, + 0x169e27f9, + 0x1024e384, + 0x62198879, + 0xd689b295, + 0xa5a340c0, + 0x8460b084, + 0x86a301c4, + 0x2e589fca, + 0xf4687ad0, + 0x8d4b4c7d, + 0x0d9635e6, + 0x91aac10f, + 0xcff70e8b, + 0x904c0678, + 0x56237892, + 0x4d8eefc5, + 0xdd1b74d2, + 0x6405fb4b, + 0x8b15cc77, + 0x83f3fca3, + 0x1ad9724c, + 0xbccceb84, + 0x18bb629d, + 0x5ae70712, + 0x6ca076d8, + 0xa231c82b, + 0x6a60573f, + 0x9046baf1, + 0x7e08ade7, + 0xd949e10a, + 0xfc5a396f, + 0x9cb8eaaa, + 0x4e050c89, + 0x751b8672, + 0x0e0d565a, + 0x837787e8, + 0xdb01db4e, + 0xb41d9bb5, + 0x41e4ce55, + 0xfe1700ae, + 0x89e70c4f, + 0x05f007b9, + 0x105a311e, + 0xa8793ba4, + 0xa7572e49, + 0xaf72e942, + 0x59f5c594, + 0x583f872b, + 0x9041d9de, + 0x72f628bd, + 0x8bb19420, + 0x957eca65, + 0x1b3bd477, + 0x581c475a, + 0x9a87bbbc, + 0x2fa9cca5, + 0x6115e020, + 0xd44f74ef, + 0x37ea131f, + 0x3f07b084, + 0x543aca7a, + 0xe91d50c6, + 0xc9139700, + 0xcd0182ac, + 0xe09514f7, + 0xfe01038e, + 0x7c97be09, + 0xbc79c28b, + 0x18aea71f, + 0xd6776f66, + 0xc020822a, + 0xd7fc90ac, + 0x382cd812, + 0x60c49263, + 0xb279295a, + 0x69eb4399, + 0x8e32fd5e, + 0xfe739807, + 0x1495d3e5, + 0xbf025c3f, + 0x190920d3, + 0x1680dbaf, + 0x1eda0681, + 0x93bac657, + 0x0e18680c, + 0x2e5d85f6, + 0x100fa070, + 0x171e7931, + 0x79f779fa, + 0x8723130d, + 0x222c2d90, + 0xbffd0448, + 0x31e7a11e, + 0x15952725, + 0x0a0d6880, + 0x2045bb27, + 0x65903721, + 0x009adfcf, + 0xc5b6017a, + 0x98920c52, + 0x960b5e3f, + 0x5bc23253, + 0x0c299c66, + 0xd0ac9e6e, + 0xf7735ce5, + 0xa4e70ec1, + 0x0b0dac09, + 0x7a5a9bfa, + 0x06001d88, + 0x316f6221, + 0x7fe9aeb1, + 0x22543edc, + 0xf8b94fde, + 0x392bf047, + 0xb0f1bc2c, + 0x984d8795, + 0xa8db0148, + 0xc42addb0, + 0x9883a82c, + 0xe8676a43, + 0x95f5ccf7, + 0x06afe12c, + 0x756a1b33, + 0x1519091b, + 0x61c5ccd2, + 0xf3288b41, + 0x7d33e180, + 0x76cc5a24, + 0xd1a18aa4, + 0xa353a07c, + 0x4e173b6b, + 0x3ad5b70c, + 0x6440b4c9, + 0x37979ae9, + 0x0c517fc6, + 0xc8252fb3, + 0x21a33062, + 0xe21e8070, + 0xa3e8fe61, + 0xb8e22e6e, + 0xd6f2fd79, + 0xc9185337, + 0xd8ef8db8, + 0x952e6ac3, + 0x2ba27d5a, + 0xe4b502d7, + 0xc720f8f4, + 0x5601e451, + 0x2dabcbf3, + 0x06d6bf4e, + 0x580e0ec5, + 0x42099aa9, + 0x288a795a, + 0x09d59ae5, + 0xc56311bf, + 0xc9a0be28, + 0x82ab89e4, + 0x63a6b7de, + 0xb654846e, + 0x53fa8bbc, + 0x766e12b2, + 0xa7a5de15, + 0x951a8fe8, + 0xa638273b, + 0x78ce2cc7, + 0x1cff0475, + 0x53318a42, + 0x1a30f362, + 0x55d14483, + 0xf19b2f8e, + 0x66a791b8, + 0xf454cc9b, + 0xc688da27, + 0x8877ee5d, + 0x7c66e45e, + 0x8fa7945b, + 0x9eb7942f, + 0xdedf49b4, + 0x22ae7a86, + 0xd2eaf279, + 0x5f7547a2, + 0x13872ebf, + 0x70ebb737, + 0x9e433f1c, + 0x40987dc1, + 0x9321c994, + 0x832871b0, + 0x77e8ebad, + 0x0a2853a2, + 0x75460864, + 0x4028c1f7, + 0x066fb1db, + 0x6a8a47dd, + 0x8ec0f102, + 0x3d9502bb, + 0x38e3b20b, + 0x1d24cebb, + 0xcd316180, + 0x2e39fcaa, + 0xd68dff5b, + 0x1b8d3990, + 0xce9715b9, + 0xcb3ef0d4, + 0xc87865ec, + 0x6eb72a87, + 0xf02302f8, + 0x9d06420c, + 0x013ada55, + 0x482dc805, + 0x469d83e4, + 0x4f64348b, + 0xb320168a, + 0x736063a3, + 0xa44e2034, + 0x14cf72d6, + 0x7758468f, + 0xdc130a50, + 0xcd3a98d1, + 0xc7d3ec32, + 0x6008c722, + 0x7729faf1, + 0xca184989, + 0xcdfbfe93, + 0x140df767, + 0xeab2b859, + 0xef388f9e, + 0xcfad00e8, + 0xb3edb3f2, + 0xd9bf19b3, + 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0x4d55a3f4, + 0x0bcb2af5, + 0xd669176e, + 0x587e3dfc, + 0x76c2cb8f, + 0xf76cf120, + 0x4d5802b4, + 0x5c14c2f2, + 0x75343fec, + 0xdd66b18c, + 0xc71afb83, + 0x98443a88, + 0xdefbb711, + 0xfdb0d451, + 0x26c463d8, + 0xbeb59073, + 0xea637d70, + 0x75ac392c, + 0x8911a2c2, + 0xea8a08c4, + 0xb17c6b41, + 0x95187ba1, + 0xca82b4e0, + 0x47b9b7c5, + 0xd07c16f8, + 0x0b008289, + 0x1638d750, + 0x1c67341e, + 0x3d1c7fcd, + 0x773a6217, + 0x402ce582, + 0xb391379f, + 0x5f329458, + 0x7df3edc8, + 0x939cb659, + 0x54cec0df, + 0x32a63ce6, + 0x5473cd21, + 0x5399ca04, + 0xd48fec8d, + 0x184a35dd, + 0x0259889e, + 0xf5de1e03, + 0xf637e932, + 0xdac59987, + 0x3482e9ef, + 0xc4b0d39c, + 0xc1703b84, + 0x82783cc5, + 0x609005de, + 0xa6f4b2ec, + 0x2cfd9aee, + 0xeeba8f38, + 0x4f1bd205, + 0xa1f30232, + 0x79587a9a, + 0x9032d2a0, + 0x3f2a3667, + 0x0be30687, + 0xab67f3b2, + 0x5e7952bd, + 0x1055730a, + 0x7326e2ef, + 0x4e90bafe, + 0x40098ae4, + 0xbc8b3245, + 0xac40eacf, + 0x990d0b6a, + 0xcc285b9d, + 0x1f84b128, + 0x3d3baa7e, + 0xa25b70c3, + 0x24ad4c19, + 0xea67f99e, + 0x0692f3a5, + 0x282a5acd, + 0x507aa6fe, + 0xb73af27f, + 0x915227cc, + 0xe3c0fb17, + 0x234d8772, + 0x5038947d, + 0xa6770fb2, + 0x0cbe5619, + 0x62310604, + 0x577f3820, + 0xa0f465d0, + 0xd58e64e3, + 0xf9c7c1a0, + 0x02366336, + 0x7514c9ff, + 0xc80e7468, + 0x31c55e4c, + 0x64f2ee36, + 0x65308077, + 0xcc8f7a9c, + 0xd5afe99c, + 0xa3d2f848, + 0xbe343aed, + 0xc9e5d1d9, + 0x7689df57, + 0x436efdb9, + 0x02fe9c78, + 0xbf44d386, + 0xd1a7f051, + 0x688f8e40, + 0xbfc35d3f, + 0x8e9ccf1d, + 0x265725ce, + 0x7b541f84, + 0x04b7534a, + 0x537689b7, + 0xf0196afd, + 0xa1c53118, + 0xdd4b8f2f, + 0x27a4542d, + 0x148fc97f, + 0xcbb1fe8e, + 0xb0f0e359, + 0x619182d1, + 0x7fe52e97, + 0x02112644, + 0xde85b69d, + 0x6ae60743, + 0xc3957d75, + 0x55ec9f1c, + 0xdf5569a7, + 0xff211f65, + 0x9f191bb7, + 0x27b4ed8e, + 0x3d6b7584, + 0x1eb61acd, + 0x5ab3edfe, + 0xb7746746, + 0xe202812e, + 0xc3a6dad6, + 0x6eadbc54, + 0xaaf3dbe5, + 0x0d5d1241, + 0x573db0ba, + 0x6acb9a75, + 0x355f4aad, + 0xb7af5481, + 0xd6895cc1, + 0x9a3576ae, + 0x0a4ce960, + 0xea88e6c0, + 0xf9777f8c, + 0xf5586085, + 0x96aa74a0, + 0x6ba5f631, + 0x98e69a66, + 0xa27317f5, + 0x7a62af6e, + 0x7c640f8c, + 0x40bdba17, + 0xc3e35f92, + 0x257c9a1c, + 0x6ae2ba67, + 0xd53319a8, + 0x82ae2cff, + 0x2b2e2602, + 0x325499f0, + 0x56415add, + 0x2f76d62a, + 0x13a4fea9, + 0x82292dfc, + 0x3452de2e, + 0x21bc5307, + 0xe8dc18ad, + 0xa1cfbcfc, + 0xa61f387b, + 0xfd781889, + 0x98e6417a, + 0x12df4516, + 0xb4946c67, + 0x0cecea65, + 0x04f28274, + 0x9df23422, + 0xb4dc8368, + 0x8e2010e2, + 0x4c304228, + 0x99918a5a, + 0x44cb62e4, + 0xe5d3f6f9, + 0xd45ab4f1, + 0x15956307, + 0x9243a7d6, + 0x0c3ee4ca, + 0xbfbc5d1b, + 0x880c3c65, + 0xe9a1e5f7, + 0x6573caae, + 0x2d971582, + 0x2931af83, + 0xfbab4eef, + 0x9b954125, + 0x16e305b1, + 0xa2aad029, + 0x0c4c4162, + 0x2d29f41e, + 0xd045716c, + 0x836fd651, + 0xb8aa8f3a, + 0x6f884795, + 0x98199e25, + 0xecc70aec, + 0xf85e31c4, + 0x0f06b850, +/* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + + diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c new file mode 100644 index 0000000000..07732198ab --- /dev/null +++ b/src/mainboard/intel/jarrell/mptable.c @@ -0,0 +1,293 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "SE7520JR20 "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_pxhd_3 = 0; + unsigned char bus_pxhd_4 = 0; + unsigned char bus_pxhd_x; + unsigned char bus_ich5r_1; + unsigned int bus_pxhd_id; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* ich5r */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1f.0, using defaults\n"); + + bus_ich5r_1 = 4; + bus_isa = 5; + } + /* pxhd-1 */ + dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n"); + + bus_pxhd_1 = 2; + } + /* pxhd-2 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_pxhd_2 = 3; + } + /* test for active riser with 2nd pxh device */ + dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); + if (dev) { + bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); + if(bus_pxhd_id == 0x35998086) { + bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS); + /* pxhd-3 */ + dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); + if(bus_pxhd_id == 0x03298086) { + bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + } + /* pxhd-4 */ + dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); + if(bus_pxhd_id == 0x032a8086) { + bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + } + } + } + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 8, 0x20, 0xfec00000); + { + struct resource *res; + device_t dev; + /* pxhd apic 3 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x09, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); + } + /* pxhd apic 4 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x0a, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); + } + /* pxhd apic 5 */ + if(bus_pxhd_3) { /* Active riser pxhd */ + dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x0b, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x); + } + } + /* pxhd apic 6 */ + if(bus_pxhd_4) { /* active riser pxhd */ + dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x0c, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x); + } + } + } + + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, 0x08, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x01, 0x08, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, 0x08, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x03, 0x08, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x04, 0x08, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x06, 0x08, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x08, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x09, 0x08, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0c, 0x08, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0d, 0x08, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0e, 0x08, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0f, 0x08, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0a, 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0b, 0x08, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0a, 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x07, 0x08, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0b, 0x08, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x05, 0x08, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0b, 0x08, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x07, 0x08, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0b, 0x08, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_isa, 0x0a, 0x08, 0x10); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + + +#warning "FIXME verify I have the irqs handled for all of the risers" + /* 2:3.0 PCI Slot 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (3<<2)|0, 0x9, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (3<<2)|1, 0x9, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (3<<2)|2, 0x9, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (3<<2)|3, 0x9, 0x4); + + + /* 3:7.0 PCI Slot 2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (7<<2)|0, 0xa, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (7<<2)|1, 0xa, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (7<<2)|2, 0xa, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (7<<2)|3, 0xa, 0x1); + + /* PCI Slot 3 (if active riser) */ + if(bus_pxhd_3) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_3, (1<<2)|0, 0xb, 0x0); + } + + /* PCI Slot 4 (if active riser) */ + if(bus_pxhd_4) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_4, (1<<2)|0, 0xc, 0x0); + } + + /* Onboard SCSI 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (5<<2)|0, 0x9, 0x2); + + /* Onboard SCSI 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_1, (5<<2)|1, 0x9, 0x1); + + /* Onboard NIC 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (4<<2)|0, 0xa, 0x6); + + /* Onboard NIC 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_pxhd_2, (4<<2)|1, 0xa, 0x7); + + /* Onboard VGA */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_ich5r_1, (12<<2)|0, 0x8, 0x11); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c new file mode 100644 index 0000000000..e9008a40dc --- /dev/null +++ b/src/mainboard/intel/jarrell/power_reset_check.c @@ -0,0 +1,12 @@ + +static void power_down_reset_check(void) +{ + uint8_t cmos; + + cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; + print_debug("Boot byte = "); + print_debug_hex8(cmos); + print_debug("\r\n"); + + if((cmos>2)&&(cmos&1)) full_reset(); +} diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/intel/jarrell/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c new file mode 100644 index 0000000000..29e8ba36f6 --- /dev/null +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -0,0 +1,138 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ICH5_WDBASE 0x400 +#define ICH5_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +} + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_jarell_frb3(void) +{ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 0); + pci_write_config16(dev, 0x04, value); + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); + base = ICH5_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Configure GPIO 48 and 40 as GPIO */ + value = inl(base + 0x30); + value |= (1 << 16) | ( 1 << 8); + outl(value, base + 0x30); + + /* Configure GPIO 48 as Output */ + value = inl(base + 0x34); + value &= ~(1 << 16); + outl(value, base + 0x34); + + /* Toggle GPIO 48 high to low */ + value = inl(base + 0x38); + value |= (1 << 16); + outl(value, base + 0x38); + value &= ~(1 << 16); + outl(value, base + 0x38); + +} + +static void disable_watchdogs(void) +{ + disable_sio_watchdog(NSC_WD_DEV); + disable_ich5_watchdog(); + disable_jarell_frb3(); + print_debug("Watchdogs disabled\r\n"); +} + +static void ich5_watchdog_on(void) +{ + device_t dev; + unsigned long value, base; + unsigned char byte; + + /* check cmos options */ + byte = cmos_read(RTC_BOOT_BYTE-1); + if(!(byte & 1)) return; /* no boot watchdog */ + byte = cmos_read(RTC_BOOT_BYTE); + if(!(byte & 2)) return; /* fallback so ignore */ + + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + /* set the time value 1 cnt = .6 sec */ + outw(0x0010, base + 0x01); + /* reload the timer with the value */ + outw(0x0001, base + 0x00); + + /* clear bit 11 in TCO1_CNT to start watchdog */ + value = inw(base + 0x08); + value &= ~(1 << 11); + outw(value, base + 0x08); + + print_debug("Watchdog ICH5 enabled\r\n"); +} diff --git a/src/mainboard/island/aruma/Config.lb b/src/mainboard/island/aruma/Config.lb index f45862d474..b05eb49045 100644 --- a/src/mainboard/island/aruma/Config.lb +++ b/src/mainboard/island/aruma/Config.lb @@ -46,6 +46,7 @@ if HAVE_ACPI_TABLES object fadt.o object dsdt.o end +object reset.o ## diff --git a/src/mainboard/island/aruma/Options.lb b/src/mainboard/island/aruma/Options.lb index fc9489a29d..87ff134cf1 100644 --- a/src/mainboard/island/aruma/Options.lb +++ b/src/mainboard/island/aruma/Options.lb @@ -4,9 +4,6 @@ uses HAVE_ACPI_TABLES uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -82,13 +79,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=0 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/island/aruma/reset.c b/src/mainboard/island/aruma/reset.c new file mode 100644 index 0000000000..7f58d01410 --- /dev/null +++ b/src/mainboard/island/aruma/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 1); +} diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index 947180d53e..506ae648e7 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -45,6 +45,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o dir /drivers/trident/blade3d diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb index d80f0c3904..37733ac803 100644 --- a/src/mainboard/newisys/khepri/Options.lb +++ b/src/mainboard/newisys/khepri/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -74,13 +71,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/newisys/khepri/reset.c b/src/mainboard/newisys/khepri/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/newisys/khepri/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb new file mode 100644 index 0000000000..8d4ada557b --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -0,0 +1,198 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can be cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7525 # mch + device pci_domain 0 on + chip southbridge/intel/esb6300 # esb6300 + register "pirq_a_d" = "0x0b0a0a05" + register "pirq_e_h" = "0x0a0b0c80" + + device pci 1c.0 on end + + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end + device pci 1d.5 on end + device pci 1d.7 on end + + device pci 1e.0 on end + + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + device pnp 2e.f off end + device pnp 2e.10 off end + device pnp 2e.14 off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 on end + end + device pci 00.0 on end + device pci 00.1 on end + device pci 00.2 on end + device pci 02.0 on end + device pci 03.0 on end + device pci 04.0 on end + device pci 08.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # cpu0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # cpu1 + device apic 6 on end + end + end +end + diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb new file mode 100644 index 0000000000..822e31f03f --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/Options.lb @@ -0,0 +1,229 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DAI" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end + diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c new file mode 100644 index 0000000000..f148a8c38b --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/auto.c @@ -0,0 +1,139 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "northbridge/intel/E7525/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7525/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0808090a +#define RECVENB_CONFIG 0x0808090a + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7525/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing 6300ESB?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 1 + dump_pci_device(PCI_DEV(0, 0x00, 0)); +// dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, 0x01000000); + /* check the first 1M in the 3rd Gig */ + ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dai_g/chip.h b/src/mainboard/supermicro/x6dai_g/chip.h new file mode 100644 index 0000000000..02f15189d6 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_supermicro_x6dai_g_ops; + +struct mainboard_supermicro_x6dai_g_config { + int nothing; +}; diff --git a/src/mainboard/supermicro/x6dai_g/cmos.layout b/src/mainboard/supermicro/x6dai_g/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/supermicro/x6dai_g/failover.c b/src/mainboard/supermicro/x6dai_g/failover.c new file mode 100644 index 0000000000..1a4a88ebfa --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7525/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/supermicro/x6dai_g/irq_tables.c b/src/mainboard/supermicro/x6dai_g/irq_tables.c new file mode 100644 index 0000000000..c34a722141 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x40163ed0 size = 272 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x122e, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x78, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, 0x00, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, + {0x00, 0x10, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00}, + {0x01, 0x00, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x04, 0x00}, + {0x00, 0x20, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00}, + {0x02, 0x00, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x06, 0x00}, + {0x00, 0xe0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00}, + {0x04, 0x08, {{0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}}, 0x01, 0x00}, + {0x04, 0x10, {{0x6a, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x07, 0x00}, + {0x04, 0x18, {{0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}}, 0x02, 0x00}, + {0x00, 0xf0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00}, + {0x05, 0x40, {{0x68, 0x1ef8}, {0x69, 0x1ef8}, {0x6a, 0x1ef8}, {0x6b, 0x1ef8}}, 0x03, 0x00}, + {0x05, 0x18, {{0x6a, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x08, 0x00}, + {0x05, 0x10, {{0x69, 0x1ef8}, {0x6a, 0x1ef8}, {0x6b, 0x1ef8}, {0x68, 0x1ef8}}, 0x05, 0x00}, + {0x00, 0xf8, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, + {0x00, 0xe8, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x6b, 0x1ef8}}, 0x00, 0x00} + } +}; diff --git a/src/mainboard/supermicro/x6dai_g/mainboard.c b/src/mainboard/supermicro/x6dai_g/mainboard.c new file mode 100644 index 0000000000..bf741989ee --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations supermicro_x6dai_g_ops = { + CHIP_NAME("Supermicro X6DAI_G mainboard ") +}; + diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c new file mode 100644 index 0000000000..9d793c44a6 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -0,0 +1,142 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "X6DAI-G "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_6300; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* southbridge */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + bus_6300 = 5; + bus_isa = 6; + } + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + /* Slot 1 function 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 4, 0x04, 0x03, 0x00); + /* Slot 2 function 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 4, 0x0c, 0x03, 0x01); + /* Slot 3 function 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_6300, 0x20, 0x02, 0x14); + /* Slot 4 function 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_6300, 0x08, 0x02, 0x15); + /* On board NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_6300, 0x0c, 0x02, 0x16); + + /* Standard local interrupt assignments */ +// smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, +// bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/supermicro/x6dai_g/reset.c b/src/mainboard/supermicro/x6dai_g/reset.c new file mode 100644 index 0000000000..1d7f5a3301 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_6300ESB_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c new file mode 100644 index 0000000000..465ba4c7b3 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -0,0 +1,42 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ICH5_WDBASE 0x400 +#define ICH5_GPIOBASE 0x500 + +static void disable_esb6300_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing 6300ESB?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_watchdogs(void) +{ + disable_esb6300_watchdog(); + print_debug("Watchdogs disabled\r\n"); +} + diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb new file mode 100644 index 0000000000..672da8233c --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -0,0 +1,220 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of LinuxBIOS will start in the boot rom +## +default _ROMBASE =( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can be cached to speed up linuxBIOS. +## execution speed. +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 # MCH + chip drivers/generic/debug # DEBUGGING + device pnp 00.0 on end + device pnp 00.1 off end + device pnp 00.2 off end + device pnp 00.3 off end + end + device pci_domain 0 on + chip southbridge/intel/esb6300 # ESB6300 + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1c.0 on + chip drivers/generic/generic + device pci 01.0 on end # onboard gige1 + device pci 02.0 on end # onboard gige2 + end + end + + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end # Southbridge Watchdog timer + device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.7 on end + + # VGA / PCI 32-bit + device pci 1e.0 on + chip drivers/generic/generic + device pci 01.0 on end + end + end + + + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 off end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end + device pci 1f.6 off end + end + + device pci 00.0 on end # Northbridge + device pci 00.1 on end # Northbridge Error reporting + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge + device pci 00.1 on end # I/O apic + device pci 00.2 on end # bridge + device pci 00.3 on end # I/O apic + end + end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end + end + + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # CPU 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # CPU 1 + device apic 6 on end + end + end +end diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb new file mode 100644 index 0000000000..d09effc37e --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/Options.lb @@ -0,0 +1,229 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DHE_g" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end + diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c new file mode 100644 index 0000000000..be5affc04c --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/auto.c @@ -0,0 +1,167 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "x6dhe_g_fixups.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0808090a +#define RECVENB_CONFIG 0x0808090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, + .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); +// mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, 0x01000000); + /* check the first 1M in the 3rd Gig */ + ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dhe_g/chip.h b/src/mainboard/supermicro/x6dhe_g/chip.h new file mode 100644 index 0000000000..f8ba112b02 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_supermicro_x6dhe_g_ops; + +struct mainboard_supermicro_x6dhe_g_config { + int nothing; +}; diff --git a/src/mainboard/supermicro/x6dhe_g/cmos.layout b/src/mainboard/supermicro/x6dhe_g/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/supermicro/x6dhe_g/failover.c b/src/mainboard/supermicro/x6dhe_g/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/supermicro/x6dhe_g/irq_tables.c b/src/mainboard/supermicro/x6dhe_g/irq_tables.c new file mode 100644 index 0000000000..0851fbe3f8 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(15*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x25a1, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00}, + {0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00} + } +}; diff --git a/src/mainboard/supermicro/x6dhe_g/mainboard.c b/src/mainboard/supermicro/x6dhe_g/mainboard.c new file mode 100644 index 0000000000..6cb224f498 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations supermicro_x6dhe_g_ops = { + CHIP_NAME("Supermicro X6DHE_G mainboard") +}; + diff --git a/src/mainboard/supermicro/x6dhe_g/microcode_updates.c b/src/mainboard/supermicro/x6dhe_g/microcode_updates.c new file mode 100644 index 0000000000..b2e72ab616 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF3413.TXT - Noconoa D-0 */
+
+ 0x00000001, /* Header Version */
+ 0x00000013, /* Patch ID */
+ 0x07302004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x95f183f0, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb2abaca8,
+ 0x6b62b8e0,
+ 0x0af32c41,
+ 0x12ca6048,
+ 0x5bd55ae6,
+ 0xb90dfc1d,
+ 0x565fe2b2,
+ 0x326b1718,
+ 0x61f3a40d,
+ 0xceb53db3,
+ 0x14fb5261,
+ 0xbb23b6c3,
+ 0x9d7c0466,
+ 0xde90a25e,
+ 0x9450e9bb,
+ 0x497bd6e4,
+ 0x97d1041a,
+ 0x1831013f,
+ 0x6e6fa37e,
+ 0x0b5c1d03,
+ 0x5eae4db2,
+ 0xc029d9e3,
+ 0x5373bca3,
+ 0xe15fccca,
+ 0x39043db0,
+ 0xaeb0ea0c,
+ 0x62b4e391,
+ 0x0b280c6b,
+ 0x279eb9d3,
+ 0x98d95ada,
+ 0xc1cb45a7,
+ 0x06917bda,
+ 0xdde8aafa,
+ 0xdff9d15c,
+ 0xd07f8f0a,
+ 0x192bcf9d,
+ 0xf77de31f,
+ 0xadf8be55,
+ 0x3f7a5d95,
+ 0x0e2140b6,
+ 0xf0c75eec,
+ 0x3254876a,
+ 0x684a1698,
+ 0x4ad0cca7,
+ 0x6d705304,
+ 0xf957d91b,
+ 0xe8bb864a,
+ 0x440d636c,
+ 0xaf4d7d06,
+ 0x12680ecf,
+ 0x5d0f9e53,
+ 0x60148a5d,
+ 0x81008364,
+ 0x243a8aed,
+ 0xd55976de,
+ 0xd6a84520,
+ 0x932d4b77,
+ 0xe67e5f19,
+ 0x7dba0e47,
+ 0xfee3b153,
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+ 0xbc0b1ce5,
+ 0xa0640cab,
+ 0x6cc20a3c,
+ 0x1c7b2524,
+ 0x4685dacc,
+ 0xeab8bb31,
+ 0x8063b5d0,
+ 0x79817d52,
+ 0x211b1972,
+ 0xd7bfc987,
+ 0xab9128dc,
+ 0x150d9b36,
+ 0x6a5838ab,
+ 0x9a0a304d,
+ 0x2e43c331,
+ 0x84f2c4b8,
+ 0x435146c1,
+ 0xed64a280,
+ 0x553ecb4c,
+ 0x5c800db2,
+ 0xeef4df95,
+ 0x5dcf2c37,
+ 0x70755ddf,
+ 0x4274737b,
+ 0xe610350e,
+ 0xd97a5997,
+ 0x7af5edce,
+ 0xfd18ba0c,
+ 0xb7587cd8,
+ 0xfa5e42d6,
+ 0x76bde9eb,
+ 0xec41eead,
+ 0x604d2423,
+ 0xb4adbcf9,
+ 0xce728fa3,
+ 0x02361c31,
+ 0x02fab64d,
+ 0x00316b1c,
+ 0x562f9aa4,
+ 0x71f85790,
+ 0x9cb6d464,
+ 0x32949ebf,
+ 0x434fc23d,
+ 0xee7fac51,
+ 0xda5cc63a,
+ 0x17e616b4,
+ 0xcd1bd1bc,
+ 0x14638cae,
+ 0xd31808fa,
+ 0xb16e0727,
+ 0xfdda2b0f,
+ 0xbc11c678,
+ 0xfe79dc6e,
+ 0xe26eefb4,
+ 0x9a78de16,
+ 0xb68f2df2,
+ 0xd47da234,
+ 0xbdff28a4,
+ 0x937bb1f4,
+ 0x0786dd46,
+ 0xbd1160f5,
+ 0xf77b070c,
+ 0x72b7c51e,
+ 0xcbb3a371,
+ 0x5e50e904,
+ 0x00fbc379,
+ 0x680757dd,
+ 0xd38193f7,
+ 0x93113e25,
+ 0x7b258da7,
+ 0x991aaa09,
+ 0xab1415be,
+ 0xa3740774,
+ 0x370b72e5,
+ 0x2fc643f4,
+ 0x3916d70e,
+ 0xea2838d3,
+ 0xe4840c42,
+ 0xd18e6959,
+ 0x69a270ee,
+ 0xee4a494e,
+ 0x0329799b,
+ 0x07480357,
+ 0x0260c46f,
+ 0x7b75346e,
+ 0x787234f4,
+ 0xe0adf25b,
+ 0xba85cacf,
+ 0xb5724eb1,
+ 0xfde2c080,
+ 0x2b6bb492,
+ 0xd2f70545,
+ 0x9ca97510,
+ 0x4034c18f,
+ 0x616bcb12,
+ 0x5667f52a,
+ 0xe2f6bfce,
+ 0x1f25969e,
+ 0x569eaab7,
+ 0x27ad8196,
+ 0x2d30a6d0,
+ 0x96d6c10a,
+ 0xcb9f024f,
+ 0x3d7941ef,
+ 0xf7a76bc5,
+ 0xe9a701d4,
+ 0xd53293a3,
+ 0x252cf5df,
+ 0xaf9172f6,
+ 0xd090c809,
+ 0xb1a17387,
+ 0x045a0987,
+ 0x92d9ffd9,
+ 0xb30c449c,
+ 0x2180ff58,
+ 0x2929f7de,
+ 0x3f91766e,
+ 0x9f488e3d,
+ 0x05dd6734,
+ 0x82482f5b,
+ 0x01da3ca2,
+ 0x42f33408,
+ 0xf8e3ba89,
+ 0x750ac2ff,
+ 0x39f11551,
+ 0x71087971,
+ 0x368fa634,
+ 0xefda0572,
+ 0x14b8f750,
+ 0xe5768705,
+ 0x71c168e2,
+ 0x8c012c63,
+ 0x12ad74ce,
+ 0x841c17ea,
+ 0xe6f44176,
+ 0x36cf2557,
+ 0x14760a6d,
+ 0x4bb3b7c2,
+ 0x14d1437d,
+ 0xbe673210,
+ 0x4d6ba9f5,
+ 0xe68abbf9,
+ 0xc311908d,
+ 0x46b63956,
+ 0xac2c9fb3,
+ 0xab769ce8,
+ 0xa29d7040,
+ 0xec3d67e3,
+ 0xdef311de,
+ 0x52a53b14,
+ 0xca924769,
+ 0xf35d1514,
+ 0x524b0471,
+ 0xc0d08591,
+ 0x454fc34c,
+ 0xca719639,
+ 0x9af2f230,
+ 0xa023a821,
+ 0x3d6539ba,
+ 0x90d0d7a2,
+ 0xc65fc56e,
+ 0x4eb2aa19,
+ 0xeba3b0e7,
+ 0x1bb5b33e,
+ 0xab8c68c2,
+ 0x0f1793d3,
+ 0xdcf176e9,
+ 0x1b7bbba0,
+ 0x96170a27,
+ 0x1955452d,
+ 0x42e88c71,
+ 0x48cad4b3,
+ 0xdcc36042,
+ 0x90619951,
+ 0x7566bc7c,
+ 0xe14ba224,
+ 0xc24ad73d,
+ 0xdb04144d,
+ 0xd9792727,
+ 0x11150943,
+ 0xe45f0c57,
+ 0xb87d184e,
+ 0x3cf13243,
+ 0x2010d95c,
+ 0x84c347c1,
+ 0x6d0f2461,
+ 0xb5c41194,
+ 0xde7ccb2e,
+ 0xb929ecb0,
+ 0x51fbd8f7,
+ 0x45dc65fb,
+ 0x6902d2c0,
+ 0xb940814f,
+ 0xf339e083,
+ 0x6f370d56,
+ 0xcaf5638e,
+ 0xe8a3cb83,
+ 0xacf414b6,
+ 0xe61095a1,
+ 0x99b4cde4,
+ 0x55112fed,
+ 0x606b9d53,
+ 0x5a05974a,
+ 0xa4c7db34,
+ 0xdc92469b,
+ 0xf9280621,
+ 0xe7b1ef95,
+ 0xc0fc5be8,
+ 0x74a1da09,
+ 0xa92a4b7f,
+ 0x3d65d75e,
+ 0xe3804335,
+ 0x1ff49e19,
+ 0x71da8170,
+ 0xac69069b,
+ 0x04aae3d5,
+ 0xc0ef4b46,
+ 0x091a3482,
+ 0x8356c7ae,
+ 0x32ecb208,
+ 0x900c89ed,
+ 0x2a206ff5,
+ 0x7eed5032,
+ 0x5b55b25d,
+ 0xf98d6df2,
+ 0xf52bc8a9,
+ 0x1aa2f5fe,
+ 0x1d33c0bf,
+ 0x3cd34e89,
+ 0x9a0da4ae,
+ 0x1c205917,
+ 0x7ca784cd,
+ 0xf7dda662,
+ 0xad97f3ff,
+ 0x525c53ec,
+ 0x024f11ff,
+ 0x32c3ae5b,
+ 0xbf372800,
+ 0x8ff15f4d,
+ 0x7605d019,
+ 0x0dae7740,
+ 0x5f5dd0ef,
+ 0x0f6c37d0,
+ 0xee6fa91e,
+ 0xb9f51051,
+ 0x39a9f0d1,
+ 0x22bf03fb,
+ 0x485a0922,
+ 0x7384b30e,
+ 0x85ba7f16,
+ 0xb1f0a524,
+ 0x7e9c5113,
+ 0x240d9306,
+ 0x1ca7b0ea,
+ 0x18a0d114,
+ 0x76b64213,
+ 0x31212cc0,
+ 0xc9dca5c3,
+ 0x69f2ae52,
+ 0x545caa7c,
+ 0xfb2ff045,
+ 0x3f3a1af5,
+ 0xe75b6913,
+ 0x775a1c79,
+ 0x4627e25f,
+ 0x90a14b97,
+ 0x06456383,
+ 0x3d52cf69,
+ 0xfb2492c3,
+ 0x39f25a22,
+ 0x81f68c55,
+ 0x87b14e15,
+ 0x0920af5d,
+ 0xe2585678,
+ 0x0671e46d,
+ 0xb77ddb67,
+ 0x3948c4b3,
+ 0x122dddef,
+ 0xd0726172,
+ 0xd3302234,
+ 0x58bab4e4,
+ 0x195ac247,
+ 0x082459f0,
+ 0x18a2566d,
+ 0xbf56078d,
+ 0x116ed409,
+ 0x5ccc0f80,
+ 0xbae0b4ca,
+ 0x21a6325d,
+ 0x7e1f0c40,
+ 0x595326d4,
+ 0x518b2244,
+ 0x8ab3cdb7,
+ 0xbe6b4835,
+ 0xfc39f8ac,
+ 0x63b167aa,
+ 0x194f070d,
+ 0xed3d0416,
+ 0xae16758a,
+ 0xb9bb6bbf,
+ 0x477d9c85,
+ 0x9808c304,
+ 0xe1d8cec4,
+ 0x7ee22e17,
+ 0x0a7a9d7f,
+ 0xcc98173a,
+ 0x5f78dc21,
+ 0x364bc95e,
+ 0xb54608d9,
+ 0x5d4d70ea,
+ 0x083a7f79,
+ 0x59ffbd73,
+ 0x4f3e9eaf,
+ 0x68755ad4,
+ 0xab254689,
+ 0x11bf09a8,
+ 0xbbc40098,
+ 0x969ca3eb,
+ 0x30eee9d2,
+ 0xe35bc37e,
+ 0xcb2d678f,
+ 0x7846876b,
+ 0xf0d28ae7,
+ 0xc092fbb2,
+ 0x321b344a,
+ 0xcc5ee81b,
+ 0xd2afa00f,
+ 0xfeccd86a,
+ 0x6e5e55c2,
+ 0x2b5543ea,
+ 0x810e4009,
+ 0xea2d8e20,
+ 0x6acae3b9,
+ 0x3828e15e,
+ 0xe1e4821c,
+ 0xf429da70,
+ 0x35f6565c,
+ 0x64b1baa8,
+ 0x350e9583,
+ 0xd2522d4f,
+ 0x5e28a3f1,
+ 0x949ff0aa,
+ 0x3c1b5694,
+ 0x146dde1f,
+ 0x6f3430e1,
+ 0x71c077b7,
+ 0x4d145924,
+ 0xe431cd28,
+ 0xb315cfde,
+ 0xa0365a4a,
+ 0x473de1aa,
+ 0xcbe4e999,
+ 0x319906e9,
+ 0xad0fea9c,
+ 0x89e4e72d,
+ 0x9dbba94d,
+ 0xd395c1c5,
+ 0xa1fff11a,
+ 0x8447e120,
+ 0xe5c59100,
+ 0xa07cb778,
+ 0x8f30a039,
+ 0xed78facb,
+ 0x86de9373,
+ 0x550c4889,
+ 0xce71e3a8,
+ 0x06167b3a,
+ 0x5abdd9a3,
+ 0xc8a9e48d,
+ 0xe3312905,
+ 0x7a63a146,
+ 0xc0f19763,
+ 0xda0cf9db,
+ 0x1d708306,
+ 0x0e41f0ba,
+ 0x4c7939fe,
+ 0x768e48c2,
+ 0xe925fd31,
+ 0x309e7870,
+ 0xfc261b87,
+ 0xc897b2de,
+ 0x6c714792,
+ 0x41c7fbac,
+ 0x57d0b3c3,
+ 0x4fa82a55,
+ 0xd56b4a87,
+ 0x81e5cabc,
+ 0xb260cb7b,
+ 0x520927ab,
+ 0x20d0ab46,
+ 0xc9f92ddf,
+ 0x81f4a21d,
+ 0xfc5a0ca2,
+ 0x95d16aad,
+ 0xe54d7847,
+ 0x6080cc07,
+ 0x0df73f7e,
+ 0xaa8d5187,
+ 0x97a0bc12,
+ 0xb22c5e68,
+ 0x0954d7dc,
+ 0x3368ab5a,
+ 0xd12541df,
+ 0x58119260,
+ 0xe5b0e1df,
+ 0x25027fa4,
+ 0x5780425d,
+ 0x29bb8791,
+ 0x4100b7a9,
+ 0x076b3519,
+ 0x15e0ebb4,
+ 0xe5fb9273,
+ 0x6dbf07e7,
+ 0x1f82bddd,
+ 0x03691b6b,
+ 0xbacef28c,
+ 0x9909ed5a,
+ 0x98886793,
+ 0x544f9a82,
+ 0x9d9749d0,
+ 0x38441606,
+ 0xc4a9f4d2,
+ 0x6ce2bcf1,
+ 0x1c7c3abd,
+ 0x62c621f1,
+ 0x871ee1e4,
+ 0xa83930ce,
+ 0xbe1ee459,
+ 0xd61f1ca4,
+ 0x8c4450e5,
+ 0x98031ca9,
+ 0xe52f54e2,
+ 0xd0c4c737,
+ 0x76074160,
+ 0xbf050c3b,
+ 0x2603af14,
+ 0x43cbb0bc,
+ 0xc631b9e8,
+ 0x26030719,
+ 0x993f570c,
+ 0xdda34038,
+ 0xe34a9793,
+ 0x337a124c,
+ 0x2aa8af16,
+ 0xf80d7473,
+ 0xf01d9397,
+ 0x68e1afb9,
+ 0x0eb37ad2,
+ 0xf71969f9,
+ 0xdf020552,
+ 0x75aa9b30,
+ 0xffa210cf,
+ 0x543c414f,
+ 0xa1e3faec,
+ 0x40891d7e,
+ 0x6b48a6c5,
+ 0xec09a1a0,
+ 0x97a31f2a,
+ 0x5a6be2d7,
+ 0xd06e492b,
+ 0xc54290af,
+ 0xcb524021,
+ 0x420e8c4d,
+ 0xfb135c17,
+ 0x2bfc8adb,
+ 0x9f0cfb46,
+ 0x564db712,
+ 0x7a97a227,
+ 0x8bb98daf,
+ 0xdd0d6180,
+ 0x3d28b9e3,
+ 0xe505050f,
+ 0x19a9868e,
+ 0x7bf5685f,
+ 0x35d698c4,
+ 0xce7e1de3,
+ 0x360a64af,
+ 0x25a1f022,
+ 0xe26c1d04,
+ 0x5b3fb364,
+ 0x932f25f7,
+ 0x9a2aa00d,
+ 0xc50fb773,
+ 0xec45ea3a,
+ 0x22ddf8e4,
+ 0xafb6a6c8,
+ 0x876d04f7,
+ 0xd9c86c3c,
+ 0xd54bee2d,
+ 0xf4e28199,
+ 0xc3456776,
+ 0x04c3107b,
+ 0xbf914e9d,
+ 0x23fefaa5,
+ 0x0931a133,
+ 0x41467758,
+ 0x8ec49707,
+ 0x5ed48709,
+ 0xd11c2de8,
+ 0xb687a0b9,
+ 0xdc908383,
+ 0xd8037ff3,
+ 0xd4311a9f,
+ 0xd00aeb6a,
+ 0xfe54df3b,
+ 0x9c51ce4d,
+ 0x36956408,
+ 0xcd28ef09,
+ 0xc68932b0,
+ 0x7c31e782,
+ 0x28b4723c,
+ 0xededacc2,
+ 0x6ddbac6b,
+ 0x775a7fc1,
+ 0x6909906f,
+ 0xa774123c,
+ 0xf63145ad,
+ 0x287b191e,
+ 0x59d79300,
+ 0xbf76a2fc,
+ 0xfbaf9207,
+ 0x2fe5b7f6,
+ 0xebe7c103,
+ 0x71ac0a8d,
+ 0x2028c3c7,
+ 0xd2cb4917,
+ 0xd74a4ee4,
+ 0xfce405d8,
+ 0xad83fd0f,
+ 0x8f9ec3da,
+ 0xaab2301c,
+ 0xc6f1339f,
+ 0xc652bced,
+ 0xe378b272,
+ 0x18e1ff34,
+ 0x9ec778b6,
+ 0xce1a3883,
+ 0x7c5e5eaf,
+ 0xd16ec37a,
+ 0xa69e45f4,
+ 0xc36cd4aa,
+ 0x045b391f,
+ 0x5a2a08f1,
+ 0x4dd8d53e,
+ 0xd64796ec,
+ 0x4476fc28,
+ 0x18dbaa50,
+ 0x00fb2407,
+ 0x177db915,
+ 0x5969758b,
+ 0x3030964a,
+ 0x81d6485b,
+ 0x7d2e12b0,
+ 0x624d6c5f,
+ 0x0746bbc0,
+ 0xe669d150,
+ 0x0465eef7,
+ 0x09764011,
+ 0x551995e4,
+ 0x8422dedf,
+ 0x0ca56194,
+ 0x293eab2e,
+ 0xf20a137a,
+ 0x55117fc2,
+ 0xbc5431af,
+ 0x064751fa,
+ 0xc0dafdb2,
+ 0x6c3b1d4f,
+ 0xeac335b3,
+ 0x71173afc,
+ 0x31c84b7c,
+ 0xfef2b4ab,
+ 0x59ca5fa2,
+ 0x664c8b4e,
+ 0x7dfd560b,
+ 0xdb0daff3,
+ 0x51f87bfa,
+ 0x58015d2e,
+ 0x67a827b4,
+ 0x62cebc1a,
+ 0x24b37298,
+ 0x75b589be,
+ 0x874f1800,
+ 0x277b795c,
+ 0xf762489e,
+ 0x87d00752,
+ 0x9be45ed1,
+ 0x296ec120,
+ 0x61162480,
+ 0x792e8a2c,
+ 0x3b631590,
+ 0xe33ba0cf,
+ 0x542ac23c,
+ 0xe1e8cffa,
+ 0xfc084cd8,
+ 0xc115ad31,
+ 0x71559928,
+ 0x791f1e33,
+ 0x662ed92b,
+ 0x7222c76d,
+ 0x02dcd566,
+ 0x8db9b4d4,
+ 0xa5f344c8,
+ 0x15806b12,
+ 0x81e572f7,
+ 0x3b3fbe25,
+ 0x2133b413,
+ 0x2d68a367,
+ 0x356f6ce7,
+ 0xcd6dfed1,
+ 0xd8b3a26e,
+ 0xe9d328da,
+ 0x127425ab,
+ 0x83a60aac,
+ 0x8cc26190,
+ 0x7f87ab26,
+ 0x56faab5f,
+ 0x76d0feaa,
+ 0x4b25dd10,
+ 0x4f6286ea,
+ 0x79298d06,
+ 0x8002bf83,
+ 0x2977c85e,
+ 0xd3b3d19a,
+ 0xa92bf132,
+ 0xa280efd8,
+ 0x83f7ad6e,
+ 0x748969c7,
+ 0x25ff411d,
+ 0x3854d3a8,
+ 0x55746aa2,
+ 0x00db5c54,
+ 0x36949e0d,
+ 0x40402ab6,
+ 0x1a720211,
+ 0xe02ce823,
+ 0x4ac104a2,
+ 0x214d2e4b,
+ 0x267e5c83,
+ 0x38a3a483,
+ 0xd1da1f67,
+ 0x0c68db2c,
+ 0xd7035d63,
+ 0xa29393bb,
+ 0xa5743519,
+ 0xcb97c84e,
+ 0xa853974f,
+ 0x147360a0,
+ 0x2df9b3f4,
+ 0x0aff129e,
+ 0x177d687f,
+ 0x87eff911,
+ 0x6c60b354,
+ 0x6c356c38,
+ 0x7d480965,
+ 0xbb06a193,
+ 0x25b0568e,
+ 0x6fd6da9a,
+ 0x82b64f14,
+ 0x3d267a78,
+ 0xf100b6a7,
+ 0x32c74539,
+ 0x6042e152,
+ 0x4548276e,
+ 0xa3a32b70,
+ 0xf029fe15,
+ 0xa9b8bd2f,
+ 0x5618eee4,
+ 0x9815a5f0,
+ 0x89fb2850,
+ 0xa9261b26,
+ 0xded9e505,
+ 0x37e9d749,
+ 0xdc4aeb78,
+ 0x9e634f7a,
+ 0xcf638d2d,
+ 0x6b679f92,
+ 0x2b64911d,
+ 0xe6d1312f,
+ 0x88b3e76a,
+ 0x56311f62,
+ 0x00916de7,
+ 0x39d0bc61,
+ 0x8ac09356,
+ 0x47abcfce,
+ 0x324cb73e,
+ 0xfadcd0a8,
+ 0x2f2fbca8,
+ 0x945eda22,
+ 0xba23cab1,
+ 0xf9fb4212,
+ 0x1fa71d45,
+ 0x867a034e,
+ 0x3bee5db1,
+ 0xf54adced,
+ 0x6633ba77,
+ 0xe1eb4f1e,
+ 0x97ef01f6,
+ 0x57fd3b32,
+ 0x5234d80d,
+ 0xe8ee95f3,
+ 0x5dc990bf,
+ 0xaba833e1,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c new file mode 100644 index 0000000000..6a284981b0 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -0,0 +1,202 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "X6DHE "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_esb6300_1; + unsigned char bus_esb6300_2; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* esb6300_2 */ + dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); + if (dev) { + bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI 0:1c.0, using defaults\n"); + + bus_esb6300_2 = 6; + } + /* esb6300_1 */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + + bus_esb6300_1 = 7; + bus_isa = 8; + } + /* pxhd-1 */ + dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n"); + + bus_pxhd_1 = 2; + } + /* pxhd-2 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_pxhd_2 = 3; + } + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + { + struct resource *res; + device_t dev; + /* PXHd apic 4 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x04, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); + printk_debug("DEBUG: Dev= %p\n", dev); + } + /* PXHd apic 5 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x05, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); + printk_debug("DEBUG: Dev= %p\n", dev); + } + } + + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, // added + bus_isa, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + 0x03, 0x08, 0x05, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + 0x03, 0x08, 0x05, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_1, 0x04, 0x03, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_1, 0x08, 0x03, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_2, 0x04, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_2, 0x08, 0x02, 0x14); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + +#warning "FIXME verify I have the irqs handled for all of the risers" + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/supermicro/x6dhe_g/reset.c b/src/mainboard/supermicro/x6dhe_g/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c new file mode 100644 index 0000000000..3904a7dc94 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -0,0 +1,99 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ESB6300_WDBASE 0x400 +#define ESB6300_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ +#if 0 + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +#endif +} + +static void disable_esb6300_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ESB6300_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_jarell_frb3(void) +{ +#if 0 + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 0); + pci_write_config16(dev, 0x04, value); + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ESB6300_GPIOBASE | 1); + base = ESB6300_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Configure GPIO 48 and 40 as GPIO */ + value = inl(base + 0x30); + value |= (1 << 16) | ( 1 << 8); + outl(value, base + 0x30); + + /* Configure GPIO 48 as Output */ + value = inl(base + 0x34); + value &= ~(1 << 16); + outl(value, base + 0x34); + + /* Toggle GPIO 48 high to low */ + value = inl(base + 0x38); + value |= (1 << 16); + outl(value, base + 0x38); + value &= ~(1 << 16); + outl(value, base + 0x38); +#endif +} + +static void disable_watchdogs(void) +{ +// disable_sio_watchdog(NSC_WD_DEV); + disable_esb6300_watchdog(); +// disable_jarell_frb3(); + print_debug("Watchdogs disabled\r\n"); +} + diff --git a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c new file mode 100644 index 0000000000..82c070b0c1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c @@ -0,0 +1,23 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + return; +} + + + + diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb new file mode 100644 index 0000000000..65a990017f --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -0,0 +1,220 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of LinuxBIOS will start in the boot rom +## +default _ROMBASE =( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can be cached to speed up linuxBIOS. +## execution speed. +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 # MCH + chip drivers/generic/debug # DEBUGGING + device pnp 00.0 off end + device pnp 00.1 off end + device pnp 00.2 off end + device pnp 00.3 off end + end + device pci_domain 0 on + chip southbridge/intel/ich5r # ICH5R + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1c.0 on + chip drivers/generic/generic + device pci 01.0 on end # onboard gige1 + device pci 02.0 on end # onboard gige2 + end + end + + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end # Southbridge Watchdog timer + device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.7 on end + + # VGA / PCI 32-bit + device pci 1e.0 on + chip drivers/generic/generic + device pci 01.0 on end + end + end + + + device pci 1f.0 on # ISA bridge + chip superio/NSC/pc87427 + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end + device pci 1f.6 off end + end + + device pci 00.0 on end # Northbridge + device pci 00.1 on end # Northbridge Error reporting + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge + device pci 00.1 on end # I/O apic + device pci 00.2 on end # bridge + device pci 00.3 on end # I/O apic + end + end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end + end + + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # CPU 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # CPU 1 + device apic 6 on end + end + end +end diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb new file mode 100644 index 0000000000..d09effc37e --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb @@ -0,0 +1,229 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DHE_g" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end + diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c new file mode 100644 index 0000000000..978356c0ee --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/auto.c @@ -0,0 +1,168 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/ich5r/ich5r_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/NSC/pc87427/pc87427.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "x6dhe_g2_fixups.c" +#include "superio/NSC/pc87427/pc87427_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0708090a +#define RECVENB_CONFIG 0x0708090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5r?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); +// mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 0 + dump_pci_devices(); +#endif +#if 1 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + //dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, 0x01000000); + /* check the first 1M in the 3rd Gig */ + ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c new file mode 100644 index 0000000000..b4966a7f18 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c @@ -0,0 +1,168 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "x6dhe_g_fixups.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0708090a +#define RECVENB_CONFIG 0x0708090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); +// mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 0 + dump_pci_devices(); +#endif +#if 1 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + //dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, 0x01000000); + /* check the first 1M in the 3rd Gig */ + ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dhe_g2/chip.h b/src/mainboard/supermicro/x6dhe_g2/chip.h new file mode 100644 index 0000000000..ff86e23bfc --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_supermicro_x6dhe_g2_ops; + +struct mainboard_supermicro_x6dhe_g2_config { + int nothing; +}; diff --git a/src/mainboard/supermicro/x6dhe_g2/cmos.layout b/src/mainboard/supermicro/x6dhe_g2/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/supermicro/x6dhe_g2/failover.c b/src/mainboard/supermicro/x6dhe_g2/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/supermicro/x6dhe_g2/irq_tables.c b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c new file mode 100644 index 0000000000..0851fbe3f8 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(15*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x25a1, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00}, + {0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00} + } +}; diff --git a/src/mainboard/supermicro/x6dhe_g2/mainboard.c b/src/mainboard/supermicro/x6dhe_g2/mainboard.c new file mode 100644 index 0000000000..dcdb6f642c --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations supermicro_x6dhe_g2_ops = { + CHIP_NAME("Supermicro X6DHE_G2 mainboard") +}; + diff --git a/src/mainboard/supermicro/x6dhe_g2/microcode_updates.c b/src/mainboard/supermicro/x6dhe_g2/microcode_updates.c new file mode 100644 index 0000000000..b2e72ab616 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF3413.TXT - Noconoa D-0 */
+
+ 0x00000001, /* Header Version */
+ 0x00000013, /* Patch ID */
+ 0x07302004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x95f183f0, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb2abaca8,
+ 0x6b62b8e0,
+ 0x0af32c41,
+ 0x12ca6048,
+ 0x5bd55ae6,
+ 0xb90dfc1d,
+ 0x565fe2b2,
+ 0x326b1718,
+ 0x61f3a40d,
+ 0xceb53db3,
+ 0x14fb5261,
+ 0xbb23b6c3,
+ 0x9d7c0466,
+ 0xde90a25e,
+ 0x9450e9bb,
+ 0x497bd6e4,
+ 0x97d1041a,
+ 0x1831013f,
+ 0x6e6fa37e,
+ 0x0b5c1d03,
+ 0x5eae4db2,
+ 0xc029d9e3,
+ 0x5373bca3,
+ 0xe15fccca,
+ 0x39043db0,
+ 0xaeb0ea0c,
+ 0x62b4e391,
+ 0x0b280c6b,
+ 0x279eb9d3,
+ 0x98d95ada,
+ 0xc1cb45a7,
+ 0x06917bda,
+ 0xdde8aafa,
+ 0xdff9d15c,
+ 0xd07f8f0a,
+ 0x192bcf9d,
+ 0xf77de31f,
+ 0xadf8be55,
+ 0x3f7a5d95,
+ 0x0e2140b6,
+ 0xf0c75eec,
+ 0x3254876a,
+ 0x684a1698,
+ 0x4ad0cca7,
+ 0x6d705304,
+ 0xf957d91b,
+ 0xe8bb864a,
+ 0x440d636c,
+ 0xaf4d7d06,
+ 0x12680ecf,
+ 0x5d0f9e53,
+ 0x60148a5d,
+ 0x81008364,
+ 0x243a8aed,
+ 0xd55976de,
+ 0xd6a84520,
+ 0x932d4b77,
+ 0xe67e5f19,
+ 0x7dba0e47,
+ 0xfee3b153,
+ 0x46b6a20c,
+ 0x2594e6f6,
+ 0x210cab0f,
+ 0xf6e47d5d,
+ 0xe38276e4,
+ 0x90fc2728,
+ 0x9faefa11,
+ 0xc972217c,
+ 0xc8d079dd,
+ 0x5f7dc338,
+ 0x106f7b7b,
+ 0xd04c0a1c,
+ 0x0eca300e,
+ 0x1ddae8a6,
+ 0x6e7fd42e,
+ 0xa56c514d,
+ 0x56a4e255,
+ 0x975ea2bf,
+ 0x0eaa78cc,
+ 0x0c3e284f,
+ 0xbacb6c71,
+ 0x1645006f,
+ 0xe9a2b955,
+ 0x0677c019,
+ 0x24b33da0,
+ 0x62f200fa,
+ 0x234238c4,
+ 0x81d5ad79,
+ 0x9f754bc9,
+ 0xeffd5016,
+ 0x041b2cc2,
+ 0x2f020bc7,
+ 0x4fcd68b8,
+ 0x22c3579c,
+ 0x4804a114,
+ 0xc42db3ea,
+ 0x7cde8141,
+ 0x47e167c8,
+ 0x01aa38cc,
+ 0x74a5c25e,
+ 0xe0c48d67,
+ 0x562365ad,
+ 0x38321e57,
+ 0x0395885a,
+ 0x6888323e,
+ 0xd6fc518f,
+ 0x1854b64c,
+ 0x06a58476,
+ 0x3662f898,
+ 0xe2bcdaee,
+ 0x84c40693,
+ 0xef09d374,
+ 0x353cc799,
+ 0x742223d4,
+ 0x05b3c99b,
+ 0x0c51ee45,
+ 0xd145824a,
+ 0xac30806c,
+ 0x2ed70c0d,
+ 0x71ae10ff,
+ 0xbf491854,
+ 0x3e1f03b4,
+ 0x76bfd6cd,
+ 0x1449aa8a,
+ 0xf954d3fb,
+ 0xf8c7c940,
+ 0x70233f85,
+ 0x0729e257,
+ 0x10bb8936,
+ 0xc35bb5b5,
+ 0x95d78b5c,
+ 0xcc1ba443,
+ 0x6f507126,
+ 0xa607cfd0,
+ 0xce22f2f3,
+ 0x5134ed8c,
+ 0xec8d2f06,
+ 0xa92413d5,
+ 0xb973f431,
+ 0x16e136dd,
+ 0xf7d41bed,
+ 0x01b002fe,
+ 0x646ed771,
+ 0x76ea3d26,
+ 0x5024af20,
+ 0x84270f51,
+ 0x9b3d7820,
+ 0x2454a2c6,
+ 0xc1f072ed,
+ 0x155e864f,
+ 0x4c39a6e5,
+ 0x928206e5,
+ 0x9d1685f5,
+ 0x45542ee7,
+ 0x1fd27d9e,
+ 0x5f2dd9ff,
+ 0x222005eb,
+ 0x354e8a55,
+ 0x1f0de29a,
+ 0xb86dc696,
+ 0x9eafafad,
+ 0x191b197e,
+ 0x0e0900e1,
+ 0xe0ac42bb,
+ 0x3143236f,
+ 0x44177def,
+ 0x05259274,
+ 0xb21af44a,
+ 0x6ddee4df,
+ 0xc7b56255,
+ 0xb6b1d39d,
+ 0x218f9070,
+ 0x96545a42,
+ 0x98cc2d4a,
+ 0xb21bac9e,
+ 0x83e12d44,
+ 0x2ef4fb39,
+ 0xbc03528f,
+ 0x9485af58,
+ 0xd9f1e6ab,
+ 0xde7607e6,
+ 0x3b398733,
+ 0x9cd9b1a9,
+ 0xabd77984,
+ 0xcce18826,
+ 0x701c5c21,
+ 0xe6591cbf,
+ 0x07a9b9e1,
+ 0x69459c90,
+ 0xe0cdcad6,
+ 0xc4c6c4b6,
+ 0x12748024,
+ 0x4a33c567,
+ 0x7d26a37e,
+ 0xcae163bf,
+ 0xeb7547fa,
+ 0xccc6a01c,
+ 0x3cb8abb8,
+ 0x64aa67b2,
+ 0x51ddf6de,
+ 0xbfe1b905,
+ 0x50923949,
+ 0xacfa43af,
+ 0x1fdb5a44,
+ 0x091533cb,
+ 0x7c92e5dc,
+ 0x1c5d0d3e,
+ 0x195271f5,
+ 0x96e73a4a,
+ 0xe1b11968,
+ 0xb42906f2,
+ 0x5a2940b3,
+ 0x611283e9,
+ 0x65829161,
+ 0x5d1357b7,
+ 0x019428ad,
+ 0x836c5c3c,
+ 0xc0e5e169,
+ 0xd360e424,
+ 0x257a9d69,
+ 0xdca09040,
+ 0x85f1c060,
+ 0xae7cae79,
+ 0xa5ddcfd6,
+ 0xdba8f68e,
+ 0xd98df596,
+ 0xe6e3cd51,
+ 0xcfb2be8f,
+ 0x368fe6cd,
+ 0x58486b75,
+ 0x791f1a48,
+ 0xf81a61f2,
+ 0x58a38155,
+ 0x30a86547,
+ 0xd7fb2db1,
+ 0x300e0b1d,
+ 0x3f838461,
+ 0xf278805a,
+ 0x49529931,
+ 0x601d5649,
+ 0xe500ba1a,
+ 0xc4f78965,
+ 0xe10ed02d,
+ 0x1f777ebd,
+ 0x2db1d17d,
+ 0x48a22e6a,
+ 0x5a14b738,
+ 0xdcf899e0,
+ 0xc845bd04,
+ 0xd04a52b9,
+ 0xf2f19b06,
+ 0xdb5ba97a,
+ 0xf05605ff,
+ 0xc787b72c,
+ 0x9f197770,
+ 0x87b31150,
+ 0x3ff00d57,
+ 0x89d1dcb3,
+ 0x07528ff4,
+ 0x4105fcef,
+ 0xb087de2e,
+ 0x3bd333a5,
+ 0x84a094f4,
+ 0x9ab8fb97,
+ 0xc9bba063,
+ 0x664c52e5,
+ 0x27fd05e4,
+ 0x3f0e491d,
+ 0xab8f4b9a,
+ 0x344a0249,
+ 0x727dd74f,
+ 0x29587211,
+ 0xbba262b9,
+ 0x319ecbb3,
+ 0xec54b023,
+ 0xd0fa096d,
+ 0x3d223f23,
+ 0x0b6013e7,
+ 0x513e045b,
+ 0xcb1edf15,
+ 0xfd44bb25,
+ 0x023eb973,
+ 0x3f55dac6,
+ 0xc2df6514,
+ 0x68589880,
+ 0x4556878e,
+ 0x86f6acfb,
+ 0xbcd23f0b,
+ 0x32c417c1,
+ 0x45f3bb56,
+ 0xbe60872b,
+ 0x09457cc0,
+ 0x2e18b62d,
+ 0x065f54d1,
+ 0xae3b4a20,
+ 0x265b10ae,
+ 0xb7547a1d,
+ 0x5a9481a9,
+ 0xd477ed02,
+ 0x601ed0fc,
+ 0x9a43257e,
+ 0xc9922b72,
+ 0xa2a696ae,
+ 0xe9d6c37b,
+ 0xfab8bdf9,
+ 0x1deb34dc,
+ 0xaa6bb090,
+ 0xbdc3b72f,
+ 0xecb3b010,
+ 0xe64376e7,
+ 0x40356095,
+ 0x928b5047,
+ 0xbd271c09,
+ 0xfd806f61,
+ 0x0821e090,
+ 0x6afb3588,
+ 0xd10e91ea,
+ 0xbbc7fedd,
+ 0xb1ac6d33,
+ 0x07788e4b,
+ 0xa10f8013,
+ 0x4f8efd9d,
+ 0xe5d8728d,
+ 0x017f3e82,
+ 0xf09ec7eb,
+ 0x6bfd7906,
+ 0xbcefcb44,
+ 0x76699ad5,
+ 0x1b976522,
+ 0xa55b3dbd,
+ 0x88bb33e2,
+ 0x98ac5b7f,
+ 0x61ac4c8b,
+ 0xfd948f3d,
+ 0xee610413,
+ 0xc77c5035,
+ 0x662825a9,
+ 0x0009fcba,
+ 0x3450fd88,
+ 0xeb391fef,
+ 0x6949960d,
+ 0x1ccb13c3,
+ 0x21dac5a6,
+ 0x6bcc6b37,
+ 0x37ad77a5,
+ 0xf71d58b1,
+ 0x84ed440d,
+ 0xe606b699,
+ 0xe43067a4,
+ 0x21d5b8b3,
+ 0xe11f83e2,
+ 0xa0cc6585,
+ 0x40eb6d16,
+ 0xc5a6879f,
+ 0xbd333fd5,
+ 0xb44acab4,
+ 0x68c016fc,
+ 0xfbcd3cfc,
+ 0xadf76e42,
+ 0xc520e516,
+ 0x7468cb61,
+ 0x585c0d52,
+ 0xea83cefe,
+ 0x615d7760,
+ 0x89c9b8fd,
+ 0x367c355a,
+ 0x409371a2,
+ 0x7edb38a7,
+ 0xca86d263,
+ 0xda18250d,
+ 0x26e1ed8b,
+ 0x02fefede,
+ 0x704cb5c8,
+ 0x52cbe1eb,
+ 0x9cdbc71a,
+ 0xa0637560,
+ 0xe31f03ca,
+ 0x2b78969b,
+ 0x803d5866,
+ 0xec52d984,
+ 0xd8df8bdb,
+ 0x6cb1d5e8,
+ 0x7b9aec01,
+ 0xf7d39401,
+ 0xdd04c6ae,
+ 0x0e5ca4eb,
+ 0x12b593c8,
+ 0x38f6d4e5,
+ 0x13a91268,
+ 0x60c8251b,
+ 0xa136cf9a,
+ 0xda070cdd,
+ 0x6142408c,
+ 0xc28065dd,
+ 0x50b73718,
+ 0x36074eee,
+ 0xc7b20fcb,
+ 0x18d29f9b,
+ 0xe97eb966,
+ 0xe6936bcc,
+ 0x1c9188ea,
+ 0x7cff40e2,
+ 0xee791ac8,
+ 0xb099a323,
+ 0x571d69b7,
+ 0x22c1f7d0,
+ 0x0b9662ee,
+ 0x76e45cb9,
+ 0xbd0d7020,
+ 0x7794bd95,
+ 0x1b0fe51a,
+ 0xda2754ef,
+ 0x7f3ad7a9,
+ 0x58f627d3,
+ 0x211670a3,
+ 0xc7471b81,
+ 0x495a93ac,
+ 0xaad4f030,
+ 0xa76614c8,
+ 0xd63dba3c,
+ 0x9c4f729c,
+ 0x6e831cfb,
+ 0xa6105c75,
+ 0x95c62188,
+ 0x723ef45d,
+ 0xf59f2dd1,
+ 0x5825283d,
+ 0x768d8a86,
+ 0x070d02ac,
+ 0xfdbcbd73,
+ 0x0d479795,
+ 0x797aa7f7,
+ 0x6c9e468b,
+ 0xa961571d,
+ 0xc7127ef0,
+ 0x4b0442e7,
+ 0xd99a9e87,
+ 0x6c876cba,
+ 0xe4f9f814,
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+ 0xfc261b87,
+ 0xc897b2de,
+ 0x6c714792,
+ 0x41c7fbac,
+ 0x57d0b3c3,
+ 0x4fa82a55,
+ 0xd56b4a87,
+ 0x81e5cabc,
+ 0xb260cb7b,
+ 0x520927ab,
+ 0x20d0ab46,
+ 0xc9f92ddf,
+ 0x81f4a21d,
+ 0xfc5a0ca2,
+ 0x95d16aad,
+ 0xe54d7847,
+ 0x6080cc07,
+ 0x0df73f7e,
+ 0xaa8d5187,
+ 0x97a0bc12,
+ 0xb22c5e68,
+ 0x0954d7dc,
+ 0x3368ab5a,
+ 0xd12541df,
+ 0x58119260,
+ 0xe5b0e1df,
+ 0x25027fa4,
+ 0x5780425d,
+ 0x29bb8791,
+ 0x4100b7a9,
+ 0x076b3519,
+ 0x15e0ebb4,
+ 0xe5fb9273,
+ 0x6dbf07e7,
+ 0x1f82bddd,
+ 0x03691b6b,
+ 0xbacef28c,
+ 0x9909ed5a,
+ 0x98886793,
+ 0x544f9a82,
+ 0x9d9749d0,
+ 0x38441606,
+ 0xc4a9f4d2,
+ 0x6ce2bcf1,
+ 0x1c7c3abd,
+ 0x62c621f1,
+ 0x871ee1e4,
+ 0xa83930ce,
+ 0xbe1ee459,
+ 0xd61f1ca4,
+ 0x8c4450e5,
+ 0x98031ca9,
+ 0xe52f54e2,
+ 0xd0c4c737,
+ 0x76074160,
+ 0xbf050c3b,
+ 0x2603af14,
+ 0x43cbb0bc,
+ 0xc631b9e8,
+ 0x26030719,
+ 0x993f570c,
+ 0xdda34038,
+ 0xe34a9793,
+ 0x337a124c,
+ 0x2aa8af16,
+ 0xf80d7473,
+ 0xf01d9397,
+ 0x68e1afb9,
+ 0x0eb37ad2,
+ 0xf71969f9,
+ 0xdf020552,
+ 0x75aa9b30,
+ 0xffa210cf,
+ 0x543c414f,
+ 0xa1e3faec,
+ 0x40891d7e,
+ 0x6b48a6c5,
+ 0xec09a1a0,
+ 0x97a31f2a,
+ 0x5a6be2d7,
+ 0xd06e492b,
+ 0xc54290af,
+ 0xcb524021,
+ 0x420e8c4d,
+ 0xfb135c17,
+ 0x2bfc8adb,
+ 0x9f0cfb46,
+ 0x564db712,
+ 0x7a97a227,
+ 0x8bb98daf,
+ 0xdd0d6180,
+ 0x3d28b9e3,
+ 0xe505050f,
+ 0x19a9868e,
+ 0x7bf5685f,
+ 0x35d698c4,
+ 0xce7e1de3,
+ 0x360a64af,
+ 0x25a1f022,
+ 0xe26c1d04,
+ 0x5b3fb364,
+ 0x932f25f7,
+ 0x9a2aa00d,
+ 0xc50fb773,
+ 0xec45ea3a,
+ 0x22ddf8e4,
+ 0xafb6a6c8,
+ 0x876d04f7,
+ 0xd9c86c3c,
+ 0xd54bee2d,
+ 0xf4e28199,
+ 0xc3456776,
+ 0x04c3107b,
+ 0xbf914e9d,
+ 0x23fefaa5,
+ 0x0931a133,
+ 0x41467758,
+ 0x8ec49707,
+ 0x5ed48709,
+ 0xd11c2de8,
+ 0xb687a0b9,
+ 0xdc908383,
+ 0xd8037ff3,
+ 0xd4311a9f,
+ 0xd00aeb6a,
+ 0xfe54df3b,
+ 0x9c51ce4d,
+ 0x36956408,
+ 0xcd28ef09,
+ 0xc68932b0,
+ 0x7c31e782,
+ 0x28b4723c,
+ 0xededacc2,
+ 0x6ddbac6b,
+ 0x775a7fc1,
+ 0x6909906f,
+ 0xa774123c,
+ 0xf63145ad,
+ 0x287b191e,
+ 0x59d79300,
+ 0xbf76a2fc,
+ 0xfbaf9207,
+ 0x2fe5b7f6,
+ 0xebe7c103,
+ 0x71ac0a8d,
+ 0x2028c3c7,
+ 0xd2cb4917,
+ 0xd74a4ee4,
+ 0xfce405d8,
+ 0xad83fd0f,
+ 0x8f9ec3da,
+ 0xaab2301c,
+ 0xc6f1339f,
+ 0xc652bced,
+ 0xe378b272,
+ 0x18e1ff34,
+ 0x9ec778b6,
+ 0xce1a3883,
+ 0x7c5e5eaf,
+ 0xd16ec37a,
+ 0xa69e45f4,
+ 0xc36cd4aa,
+ 0x045b391f,
+ 0x5a2a08f1,
+ 0x4dd8d53e,
+ 0xd64796ec,
+ 0x4476fc28,
+ 0x18dbaa50,
+ 0x00fb2407,
+ 0x177db915,
+ 0x5969758b,
+ 0x3030964a,
+ 0x81d6485b,
+ 0x7d2e12b0,
+ 0x624d6c5f,
+ 0x0746bbc0,
+ 0xe669d150,
+ 0x0465eef7,
+ 0x09764011,
+ 0x551995e4,
+ 0x8422dedf,
+ 0x0ca56194,
+ 0x293eab2e,
+ 0xf20a137a,
+ 0x55117fc2,
+ 0xbc5431af,
+ 0x064751fa,
+ 0xc0dafdb2,
+ 0x6c3b1d4f,
+ 0xeac335b3,
+ 0x71173afc,
+ 0x31c84b7c,
+ 0xfef2b4ab,
+ 0x59ca5fa2,
+ 0x664c8b4e,
+ 0x7dfd560b,
+ 0xdb0daff3,
+ 0x51f87bfa,
+ 0x58015d2e,
+ 0x67a827b4,
+ 0x62cebc1a,
+ 0x24b37298,
+ 0x75b589be,
+ 0x874f1800,
+ 0x277b795c,
+ 0xf762489e,
+ 0x87d00752,
+ 0x9be45ed1,
+ 0x296ec120,
+ 0x61162480,
+ 0x792e8a2c,
+ 0x3b631590,
+ 0xe33ba0cf,
+ 0x542ac23c,
+ 0xe1e8cffa,
+ 0xfc084cd8,
+ 0xc115ad31,
+ 0x71559928,
+ 0x791f1e33,
+ 0x662ed92b,
+ 0x7222c76d,
+ 0x02dcd566,
+ 0x8db9b4d4,
+ 0xa5f344c8,
+ 0x15806b12,
+ 0x81e572f7,
+ 0x3b3fbe25,
+ 0x2133b413,
+ 0x2d68a367,
+ 0x356f6ce7,
+ 0xcd6dfed1,
+ 0xd8b3a26e,
+ 0xe9d328da,
+ 0x127425ab,
+ 0x83a60aac,
+ 0x8cc26190,
+ 0x7f87ab26,
+ 0x56faab5f,
+ 0x76d0feaa,
+ 0x4b25dd10,
+ 0x4f6286ea,
+ 0x79298d06,
+ 0x8002bf83,
+ 0x2977c85e,
+ 0xd3b3d19a,
+ 0xa92bf132,
+ 0xa280efd8,
+ 0x83f7ad6e,
+ 0x748969c7,
+ 0x25ff411d,
+ 0x3854d3a8,
+ 0x55746aa2,
+ 0x00db5c54,
+ 0x36949e0d,
+ 0x40402ab6,
+ 0x1a720211,
+ 0xe02ce823,
+ 0x4ac104a2,
+ 0x214d2e4b,
+ 0x267e5c83,
+ 0x38a3a483,
+ 0xd1da1f67,
+ 0x0c68db2c,
+ 0xd7035d63,
+ 0xa29393bb,
+ 0xa5743519,
+ 0xcb97c84e,
+ 0xa853974f,
+ 0x147360a0,
+ 0x2df9b3f4,
+ 0x0aff129e,
+ 0x177d687f,
+ 0x87eff911,
+ 0x6c60b354,
+ 0x6c356c38,
+ 0x7d480965,
+ 0xbb06a193,
+ 0x25b0568e,
+ 0x6fd6da9a,
+ 0x82b64f14,
+ 0x3d267a78,
+ 0xf100b6a7,
+ 0x32c74539,
+ 0x6042e152,
+ 0x4548276e,
+ 0xa3a32b70,
+ 0xf029fe15,
+ 0xa9b8bd2f,
+ 0x5618eee4,
+ 0x9815a5f0,
+ 0x89fb2850,
+ 0xa9261b26,
+ 0xded9e505,
+ 0x37e9d749,
+ 0xdc4aeb78,
+ 0x9e634f7a,
+ 0xcf638d2d,
+ 0x6b679f92,
+ 0x2b64911d,
+ 0xe6d1312f,
+ 0x88b3e76a,
+ 0x56311f62,
+ 0x00916de7,
+ 0x39d0bc61,
+ 0x8ac09356,
+ 0x47abcfce,
+ 0x324cb73e,
+ 0xfadcd0a8,
+ 0x2f2fbca8,
+ 0x945eda22,
+ 0xba23cab1,
+ 0xf9fb4212,
+ 0x1fa71d45,
+ 0x867a034e,
+ 0x3bee5db1,
+ 0xf54adced,
+ 0x6633ba77,
+ 0xe1eb4f1e,
+ 0x97ef01f6,
+ 0x57fd3b32,
+ 0x5234d80d,
+ 0xe8ee95f3,
+ 0x5dc990bf,
+ 0xaba833e1,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c new file mode 100644 index 0000000000..6a284981b0 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -0,0 +1,202 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "X6DHE "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_esb6300_1; + unsigned char bus_esb6300_2; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* esb6300_2 */ + dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); + if (dev) { + bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI 0:1c.0, using defaults\n"); + + bus_esb6300_2 = 6; + } + /* esb6300_1 */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + + bus_esb6300_1 = 7; + bus_isa = 8; + } + /* pxhd-1 */ + dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n"); + + bus_pxhd_1 = 2; + } + /* pxhd-2 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_pxhd_2 = 3; + } + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + { + struct resource *res; + device_t dev; + /* PXHd apic 4 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x04, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); + printk_debug("DEBUG: Dev= %p\n", dev); + } + /* PXHd apic 5 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x05, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); + printk_debug("DEBUG: Dev= %p\n", dev); + } + } + + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, // added + bus_isa, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + 0x03, 0x08, 0x05, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + 0x03, 0x08, 0x05, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_1, 0x04, 0x03, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_1, 0x08, 0x03, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_2, 0x04, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added + bus_esb6300_2, 0x08, 0x02, 0x14); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + +#warning "FIXME verify I have the irqs handled for all of the risers" + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/supermicro/x6dhe_g2/reset.c b/src/mainboard/supermicro/x6dhe_g2/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c new file mode 100644 index 0000000000..3904a7dc94 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -0,0 +1,99 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ESB6300_WDBASE 0x400 +#define ESB6300_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ +#if 0 + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +#endif +} + +static void disable_esb6300_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ESB6300_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_jarell_frb3(void) +{ +#if 0 + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing esb6300?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 0); + pci_write_config16(dev, 0x04, value); + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ESB6300_GPIOBASE | 1); + base = ESB6300_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Configure GPIO 48 and 40 as GPIO */ + value = inl(base + 0x30); + value |= (1 << 16) | ( 1 << 8); + outl(value, base + 0x30); + + /* Configure GPIO 48 as Output */ + value = inl(base + 0x34); + value &= ~(1 << 16); + outl(value, base + 0x34); + + /* Toggle GPIO 48 high to low */ + value = inl(base + 0x38); + value |= (1 << 16); + outl(value, base + 0x38); + value &= ~(1 << 16); + outl(value, base + 0x38); +#endif +} + +static void disable_watchdogs(void) +{ +// disable_sio_watchdog(NSC_WD_DEV); + disable_esb6300_watchdog(); +// disable_jarell_frb3(); + print_debug("Watchdogs disabled\r\n"); +} + diff --git a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c new file mode 100644 index 0000000000..82c070b0c1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c @@ -0,0 +1,23 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + return; +} + + + + diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb new file mode 100644 index 0000000000..e6cdc0c5f9 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -0,0 +1,218 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 # mch + device pci_domain 0 on + chip southbridge/intel/ich5r # ich5r + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> VGA + device pci 1e.0 on end + + # -> IDE + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on end + device pci 03.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 2 + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on + # On board gig e1000 + chip drivers/generic/generic + device pci 02.0 on end + device pci 02.1 on end + end + end + device pci 0.3 on end + end + end + device pci 04.0 on + chip southbridge/intel/pxhd # pxhd2 + # Bus bridges and ioapics usually bus 5 + device pci 0.0 on end + # Slot 6 is usually 6:2.0 + device pci 0.1 on end + device pci 0.2 on end + # Slot 7 is usually 7:2.0 + device pci 0.3 on end + end + end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070105" +end + diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb new file mode 100644 index 0000000000..8461cdb7d1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb @@ -0,0 +1,228 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DHR" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c new file mode 100644 index 0000000000..ce729546e6 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/auto.c @@ -0,0 +1,169 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/ich5r/ich5r_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "x6dhr_fixups.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D0F0 | \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0808090a +#define RECVENB_CONFIG 0x0808090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); + mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 1 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x00100000, 0x01000000); + ram_check(0x00100000, 0x00100100); + /* check the first 1M in the 3rd Gig */ +// ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dhr_ig/chip.h b/src/mainboard/supermicro/x6dhr_ig/chip.h new file mode 100644 index 0000000000..495788e43c --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_supermicro_x6dhr_ig_ops; + +struct mainboard_supermicro_x6dhr_ig_config { + int nothing; +}; diff --git a/src/mainboard/supermicro/x6dhr_ig/cmos.layout b/src/mainboard/supermicro/x6dhr_ig/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/supermicro/x6dhr_ig/failover.c b/src/mainboard/supermicro/x6dhr_ig/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/supermicro/x6dhr_ig/irq_tables.c b/src/mainboard/supermicro/x6dhr_ig/irq_tables.c new file mode 100644 index 0000000000..5ed51feaa1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(15*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x24d0, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00}, + {0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00} + } +}; diff --git a/src/mainboard/supermicro/x6dhr_ig/mainboard.c b/src/mainboard/supermicro/x6dhr_ig/mainboard.c new file mode 100644 index 0000000000..cae000d5c7 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations mainboard_supermicro_x6dhr_ig_ops = { + CHIP_NAME("Supermicro x6dhr-ig") +}; + diff --git a/src/mainboard/supermicro/x6dhr_ig/microcode_updates.c b/src/mainboard/supermicro/x6dhr_ig/microcode_updates.c new file mode 100644 index 0000000000..b2e72ab616 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF3413.TXT - Noconoa D-0 */
+
+ 0x00000001, /* Header Version */
+ 0x00000013, /* Patch ID */
+ 0x07302004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x95f183f0, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb2abaca8,
+ 0x6b62b8e0,
+ 0x0af32c41,
+ 0x12ca6048,
+ 0x5bd55ae6,
+ 0xb90dfc1d,
+ 0x565fe2b2,
+ 0x326b1718,
+ 0x61f3a40d,
+ 0xceb53db3,
+ 0x14fb5261,
+ 0xbb23b6c3,
+ 0x9d7c0466,
+ 0xde90a25e,
+ 0x9450e9bb,
+ 0x497bd6e4,
+ 0x97d1041a,
+ 0x1831013f,
+ 0x6e6fa37e,
+ 0x0b5c1d03,
+ 0x5eae4db2,
+ 0xc029d9e3,
+ 0x5373bca3,
+ 0xe15fccca,
+ 0x39043db0,
+ 0xaeb0ea0c,
+ 0x62b4e391,
+ 0x0b280c6b,
+ 0x279eb9d3,
+ 0x98d95ada,
+ 0xc1cb45a7,
+ 0x06917bda,
+ 0xdde8aafa,
+ 0xdff9d15c,
+ 0xd07f8f0a,
+ 0x192bcf9d,
+ 0xf77de31f,
+ 0xadf8be55,
+ 0x3f7a5d95,
+ 0x0e2140b6,
+ 0xf0c75eec,
+ 0x3254876a,
+ 0x684a1698,
+ 0x4ad0cca7,
+ 0x6d705304,
+ 0xf957d91b,
+ 0xe8bb864a,
+ 0x440d636c,
+ 0xaf4d7d06,
+ 0x12680ecf,
+ 0x5d0f9e53,
+ 0x60148a5d,
+ 0x81008364,
+ 0x243a8aed,
+ 0xd55976de,
+ 0xd6a84520,
+ 0x932d4b77,
+ 0xe67e5f19,
+ 0x7dba0e47,
+ 0xfee3b153,
+ 0x46b6a20c,
+ 0x2594e6f6,
+ 0x210cab0f,
+ 0xf6e47d5d,
+ 0xe38276e4,
+ 0x90fc2728,
+ 0x9faefa11,
+ 0xc972217c,
+ 0xc8d079dd,
+ 0x5f7dc338,
+ 0x106f7b7b,
+ 0xd04c0a1c,
+ 0x0eca300e,
+ 0x1ddae8a6,
+ 0x6e7fd42e,
+ 0xa56c514d,
+ 0x56a4e255,
+ 0x975ea2bf,
+ 0x0eaa78cc,
+ 0x0c3e284f,
+ 0xbacb6c71,
+ 0x1645006f,
+ 0xe9a2b955,
+ 0x0677c019,
+ 0x24b33da0,
+ 0x62f200fa,
+ 0x234238c4,
+ 0x81d5ad79,
+ 0x9f754bc9,
+ 0xeffd5016,
+ 0x041b2cc2,
+ 0x2f020bc7,
+ 0x4fcd68b8,
+ 0x22c3579c,
+ 0x4804a114,
+ 0xc42db3ea,
+ 0x7cde8141,
+ 0x47e167c8,
+ 0x01aa38cc,
+ 0x74a5c25e,
+ 0xe0c48d67,
+ 0x562365ad,
+ 0x38321e57,
+ 0x0395885a,
+ 0x6888323e,
+ 0xd6fc518f,
+ 0x1854b64c,
+ 0x06a58476,
+ 0x3662f898,
+ 0xe2bcdaee,
+ 0x84c40693,
+ 0xef09d374,
+ 0x353cc799,
+ 0x742223d4,
+ 0x05b3c99b,
+ 0x0c51ee45,
+ 0xd145824a,
+ 0xac30806c,
+ 0x2ed70c0d,
+ 0x71ae10ff,
+ 0xbf491854,
+ 0x3e1f03b4,
+ 0x76bfd6cd,
+ 0x1449aa8a,
+ 0xf954d3fb,
+ 0xf8c7c940,
+ 0x70233f85,
+ 0x0729e257,
+ 0x10bb8936,
+ 0xc35bb5b5,
+ 0x95d78b5c,
+ 0xcc1ba443,
+ 0x6f507126,
+ 0xa607cfd0,
+ 0xce22f2f3,
+ 0x5134ed8c,
+ 0xec8d2f06,
+ 0xa92413d5,
+ 0xb973f431,
+ 0x16e136dd,
+ 0xf7d41bed,
+ 0x01b002fe,
+ 0x646ed771,
+ 0x76ea3d26,
+ 0x5024af20,
+ 0x84270f51,
+ 0x9b3d7820,
+ 0x2454a2c6,
+ 0xc1f072ed,
+ 0x155e864f,
+ 0x4c39a6e5,
+ 0x928206e5,
+ 0x9d1685f5,
+ 0x45542ee7,
+ 0x1fd27d9e,
+ 0x5f2dd9ff,
+ 0x222005eb,
+ 0x354e8a55,
+ 0x1f0de29a,
+ 0xb86dc696,
+ 0x9eafafad,
+ 0x191b197e,
+ 0x0e0900e1,
+ 0xe0ac42bb,
+ 0x3143236f,
+ 0x44177def,
+ 0x05259274,
+ 0xb21af44a,
+ 0x6ddee4df,
+ 0xc7b56255,
+ 0xb6b1d39d,
+ 0x218f9070,
+ 0x96545a42,
+ 0x98cc2d4a,
+ 0xb21bac9e,
+ 0x83e12d44,
+ 0x2ef4fb39,
+ 0xbc03528f,
+ 0x9485af58,
+ 0xd9f1e6ab,
+ 0xde7607e6,
+ 0x3b398733,
+ 0x9cd9b1a9,
+ 0xabd77984,
+ 0xcce18826,
+ 0x701c5c21,
+ 0xe6591cbf,
+ 0x07a9b9e1,
+ 0x69459c90,
+ 0xe0cdcad6,
+ 0xc4c6c4b6,
+ 0x12748024,
+ 0x4a33c567,
+ 0x7d26a37e,
+ 0xcae163bf,
+ 0xeb7547fa,
+ 0xccc6a01c,
+ 0x3cb8abb8,
+ 0x64aa67b2,
+ 0x51ddf6de,
+ 0xbfe1b905,
+ 0x50923949,
+ 0xacfa43af,
+ 0x1fdb5a44,
+ 0x091533cb,
+ 0x7c92e5dc,
+ 0x1c5d0d3e,
+ 0x195271f5,
+ 0x96e73a4a,
+ 0xe1b11968,
+ 0xb42906f2,
+ 0x5a2940b3,
+ 0x611283e9,
+ 0x65829161,
+ 0x5d1357b7,
+ 0x019428ad,
+ 0x836c5c3c,
+ 0xc0e5e169,
+ 0xd360e424,
+ 0x257a9d69,
+ 0xdca09040,
+ 0x85f1c060,
+ 0xae7cae79,
+ 0xa5ddcfd6,
+ 0xdba8f68e,
+ 0xd98df596,
+ 0xe6e3cd51,
+ 0xcfb2be8f,
+ 0x368fe6cd,
+ 0x58486b75,
+ 0x791f1a48,
+ 0xf81a61f2,
+ 0x58a38155,
+ 0x30a86547,
+ 0xd7fb2db1,
+ 0x300e0b1d,
+ 0x3f838461,
+ 0xf278805a,
+ 0x49529931,
+ 0x601d5649,
+ 0xe500ba1a,
+ 0xc4f78965,
+ 0xe10ed02d,
+ 0x1f777ebd,
+ 0x2db1d17d,
+ 0x48a22e6a,
+ 0x5a14b738,
+ 0xdcf899e0,
+ 0xc845bd04,
+ 0xd04a52b9,
+ 0xf2f19b06,
+ 0xdb5ba97a,
+ 0xf05605ff,
+ 0xc787b72c,
+ 0x9f197770,
+ 0x87b31150,
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+ 0x99b4cde4,
+ 0x55112fed,
+ 0x606b9d53,
+ 0x5a05974a,
+ 0xa4c7db34,
+ 0xdc92469b,
+ 0xf9280621,
+ 0xe7b1ef95,
+ 0xc0fc5be8,
+ 0x74a1da09,
+ 0xa92a4b7f,
+ 0x3d65d75e,
+ 0xe3804335,
+ 0x1ff49e19,
+ 0x71da8170,
+ 0xac69069b,
+ 0x04aae3d5,
+ 0xc0ef4b46,
+ 0x091a3482,
+ 0x8356c7ae,
+ 0x32ecb208,
+ 0x900c89ed,
+ 0x2a206ff5,
+ 0x7eed5032,
+ 0x5b55b25d,
+ 0xf98d6df2,
+ 0xf52bc8a9,
+ 0x1aa2f5fe,
+ 0x1d33c0bf,
+ 0x3cd34e89,
+ 0x9a0da4ae,
+ 0x1c205917,
+ 0x7ca784cd,
+ 0xf7dda662,
+ 0xad97f3ff,
+ 0x525c53ec,
+ 0x024f11ff,
+ 0x32c3ae5b,
+ 0xbf372800,
+ 0x8ff15f4d,
+ 0x7605d019,
+ 0x0dae7740,
+ 0x5f5dd0ef,
+ 0x0f6c37d0,
+ 0xee6fa91e,
+ 0xb9f51051,
+ 0x39a9f0d1,
+ 0x22bf03fb,
+ 0x485a0922,
+ 0x7384b30e,
+ 0x85ba7f16,
+ 0xb1f0a524,
+ 0x7e9c5113,
+ 0x240d9306,
+ 0x1ca7b0ea,
+ 0x18a0d114,
+ 0x76b64213,
+ 0x31212cc0,
+ 0xc9dca5c3,
+ 0x69f2ae52,
+ 0x545caa7c,
+ 0xfb2ff045,
+ 0x3f3a1af5,
+ 0xe75b6913,
+ 0x775a1c79,
+ 0x4627e25f,
+ 0x90a14b97,
+ 0x06456383,
+ 0x3d52cf69,
+ 0xfb2492c3,
+ 0x39f25a22,
+ 0x81f68c55,
+ 0x87b14e15,
+ 0x0920af5d,
+ 0xe2585678,
+ 0x0671e46d,
+ 0xb77ddb67,
+ 0x3948c4b3,
+ 0x122dddef,
+ 0xd0726172,
+ 0xd3302234,
+ 0x58bab4e4,
+ 0x195ac247,
+ 0x082459f0,
+ 0x18a2566d,
+ 0xbf56078d,
+ 0x116ed409,
+ 0x5ccc0f80,
+ 0xbae0b4ca,
+ 0x21a6325d,
+ 0x7e1f0c40,
+ 0x595326d4,
+ 0x518b2244,
+ 0x8ab3cdb7,
+ 0xbe6b4835,
+ 0xfc39f8ac,
+ 0x63b167aa,
+ 0x194f070d,
+ 0xed3d0416,
+ 0xae16758a,
+ 0xb9bb6bbf,
+ 0x477d9c85,
+ 0x9808c304,
+ 0xe1d8cec4,
+ 0x7ee22e17,
+ 0x0a7a9d7f,
+ 0xcc98173a,
+ 0x5f78dc21,
+ 0x364bc95e,
+ 0xb54608d9,
+ 0x5d4d70ea,
+ 0x083a7f79,
+ 0x59ffbd73,
+ 0x4f3e9eaf,
+ 0x68755ad4,
+ 0xab254689,
+ 0x11bf09a8,
+ 0xbbc40098,
+ 0x969ca3eb,
+ 0x30eee9d2,
+ 0xe35bc37e,
+ 0xcb2d678f,
+ 0x7846876b,
+ 0xf0d28ae7,
+ 0xc092fbb2,
+ 0x321b344a,
+ 0xcc5ee81b,
+ 0xd2afa00f,
+ 0xfeccd86a,
+ 0x6e5e55c2,
+ 0x2b5543ea,
+ 0x810e4009,
+ 0xea2d8e20,
+ 0x6acae3b9,
+ 0x3828e15e,
+ 0xe1e4821c,
+ 0xf429da70,
+ 0x35f6565c,
+ 0x64b1baa8,
+ 0x350e9583,
+ 0xd2522d4f,
+ 0x5e28a3f1,
+ 0x949ff0aa,
+ 0x3c1b5694,
+ 0x146dde1f,
+ 0x6f3430e1,
+ 0x71c077b7,
+ 0x4d145924,
+ 0xe431cd28,
+ 0xb315cfde,
+ 0xa0365a4a,
+ 0x473de1aa,
+ 0xcbe4e999,
+ 0x319906e9,
+ 0xad0fea9c,
+ 0x89e4e72d,
+ 0x9dbba94d,
+ 0xd395c1c5,
+ 0xa1fff11a,
+ 0x8447e120,
+ 0xe5c59100,
+ 0xa07cb778,
+ 0x8f30a039,
+ 0xed78facb,
+ 0x86de9373,
+ 0x550c4889,
+ 0xce71e3a8,
+ 0x06167b3a,
+ 0x5abdd9a3,
+ 0xc8a9e48d,
+ 0xe3312905,
+ 0x7a63a146,
+ 0xc0f19763,
+ 0xda0cf9db,
+ 0x1d708306,
+ 0x0e41f0ba,
+ 0x4c7939fe,
+ 0x768e48c2,
+ 0xe925fd31,
+ 0x309e7870,
+ 0xfc261b87,
+ 0xc897b2de,
+ 0x6c714792,
+ 0x41c7fbac,
+ 0x57d0b3c3,
+ 0x4fa82a55,
+ 0xd56b4a87,
+ 0x81e5cabc,
+ 0xb260cb7b,
+ 0x520927ab,
+ 0x20d0ab46,
+ 0xc9f92ddf,
+ 0x81f4a21d,
+ 0xfc5a0ca2,
+ 0x95d16aad,
+ 0xe54d7847,
+ 0x6080cc07,
+ 0x0df73f7e,
+ 0xaa8d5187,
+ 0x97a0bc12,
+ 0xb22c5e68,
+ 0x0954d7dc,
+ 0x3368ab5a,
+ 0xd12541df,
+ 0x58119260,
+ 0xe5b0e1df,
+ 0x25027fa4,
+ 0x5780425d,
+ 0x29bb8791,
+ 0x4100b7a9,
+ 0x076b3519,
+ 0x15e0ebb4,
+ 0xe5fb9273,
+ 0x6dbf07e7,
+ 0x1f82bddd,
+ 0x03691b6b,
+ 0xbacef28c,
+ 0x9909ed5a,
+ 0x98886793,
+ 0x544f9a82,
+ 0x9d9749d0,
+ 0x38441606,
+ 0xc4a9f4d2,
+ 0x6ce2bcf1,
+ 0x1c7c3abd,
+ 0x62c621f1,
+ 0x871ee1e4,
+ 0xa83930ce,
+ 0xbe1ee459,
+ 0xd61f1ca4,
+ 0x8c4450e5,
+ 0x98031ca9,
+ 0xe52f54e2,
+ 0xd0c4c737,
+ 0x76074160,
+ 0xbf050c3b,
+ 0x2603af14,
+ 0x43cbb0bc,
+ 0xc631b9e8,
+ 0x26030719,
+ 0x993f570c,
+ 0xdda34038,
+ 0xe34a9793,
+ 0x337a124c,
+ 0x2aa8af16,
+ 0xf80d7473,
+ 0xf01d9397,
+ 0x68e1afb9,
+ 0x0eb37ad2,
+ 0xf71969f9,
+ 0xdf020552,
+ 0x75aa9b30,
+ 0xffa210cf,
+ 0x543c414f,
+ 0xa1e3faec,
+ 0x40891d7e,
+ 0x6b48a6c5,
+ 0xec09a1a0,
+ 0x97a31f2a,
+ 0x5a6be2d7,
+ 0xd06e492b,
+ 0xc54290af,
+ 0xcb524021,
+ 0x420e8c4d,
+ 0xfb135c17,
+ 0x2bfc8adb,
+ 0x9f0cfb46,
+ 0x564db712,
+ 0x7a97a227,
+ 0x8bb98daf,
+ 0xdd0d6180,
+ 0x3d28b9e3,
+ 0xe505050f,
+ 0x19a9868e,
+ 0x7bf5685f,
+ 0x35d698c4,
+ 0xce7e1de3,
+ 0x360a64af,
+ 0x25a1f022,
+ 0xe26c1d04,
+ 0x5b3fb364,
+ 0x932f25f7,
+ 0x9a2aa00d,
+ 0xc50fb773,
+ 0xec45ea3a,
+ 0x22ddf8e4,
+ 0xafb6a6c8,
+ 0x876d04f7,
+ 0xd9c86c3c,
+ 0xd54bee2d,
+ 0xf4e28199,
+ 0xc3456776,
+ 0x04c3107b,
+ 0xbf914e9d,
+ 0x23fefaa5,
+ 0x0931a133,
+ 0x41467758,
+ 0x8ec49707,
+ 0x5ed48709,
+ 0xd11c2de8,
+ 0xb687a0b9,
+ 0xdc908383,
+ 0xd8037ff3,
+ 0xd4311a9f,
+ 0xd00aeb6a,
+ 0xfe54df3b,
+ 0x9c51ce4d,
+ 0x36956408,
+ 0xcd28ef09,
+ 0xc68932b0,
+ 0x7c31e782,
+ 0x28b4723c,
+ 0xededacc2,
+ 0x6ddbac6b,
+ 0x775a7fc1,
+ 0x6909906f,
+ 0xa774123c,
+ 0xf63145ad,
+ 0x287b191e,
+ 0x59d79300,
+ 0xbf76a2fc,
+ 0xfbaf9207,
+ 0x2fe5b7f6,
+ 0xebe7c103,
+ 0x71ac0a8d,
+ 0x2028c3c7,
+ 0xd2cb4917,
+ 0xd74a4ee4,
+ 0xfce405d8,
+ 0xad83fd0f,
+ 0x8f9ec3da,
+ 0xaab2301c,
+ 0xc6f1339f,
+ 0xc652bced,
+ 0xe378b272,
+ 0x18e1ff34,
+ 0x9ec778b6,
+ 0xce1a3883,
+ 0x7c5e5eaf,
+ 0xd16ec37a,
+ 0xa69e45f4,
+ 0xc36cd4aa,
+ 0x045b391f,
+ 0x5a2a08f1,
+ 0x4dd8d53e,
+ 0xd64796ec,
+ 0x4476fc28,
+ 0x18dbaa50,
+ 0x00fb2407,
+ 0x177db915,
+ 0x5969758b,
+ 0x3030964a,
+ 0x81d6485b,
+ 0x7d2e12b0,
+ 0x624d6c5f,
+ 0x0746bbc0,
+ 0xe669d150,
+ 0x0465eef7,
+ 0x09764011,
+ 0x551995e4,
+ 0x8422dedf,
+ 0x0ca56194,
+ 0x293eab2e,
+ 0xf20a137a,
+ 0x55117fc2,
+ 0xbc5431af,
+ 0x064751fa,
+ 0xc0dafdb2,
+ 0x6c3b1d4f,
+ 0xeac335b3,
+ 0x71173afc,
+ 0x31c84b7c,
+ 0xfef2b4ab,
+ 0x59ca5fa2,
+ 0x664c8b4e,
+ 0x7dfd560b,
+ 0xdb0daff3,
+ 0x51f87bfa,
+ 0x58015d2e,
+ 0x67a827b4,
+ 0x62cebc1a,
+ 0x24b37298,
+ 0x75b589be,
+ 0x874f1800,
+ 0x277b795c,
+ 0xf762489e,
+ 0x87d00752,
+ 0x9be45ed1,
+ 0x296ec120,
+ 0x61162480,
+ 0x792e8a2c,
+ 0x3b631590,
+ 0xe33ba0cf,
+ 0x542ac23c,
+ 0xe1e8cffa,
+ 0xfc084cd8,
+ 0xc115ad31,
+ 0x71559928,
+ 0x791f1e33,
+ 0x662ed92b,
+ 0x7222c76d,
+ 0x02dcd566,
+ 0x8db9b4d4,
+ 0xa5f344c8,
+ 0x15806b12,
+ 0x81e572f7,
+ 0x3b3fbe25,
+ 0x2133b413,
+ 0x2d68a367,
+ 0x356f6ce7,
+ 0xcd6dfed1,
+ 0xd8b3a26e,
+ 0xe9d328da,
+ 0x127425ab,
+ 0x83a60aac,
+ 0x8cc26190,
+ 0x7f87ab26,
+ 0x56faab5f,
+ 0x76d0feaa,
+ 0x4b25dd10,
+ 0x4f6286ea,
+ 0x79298d06,
+ 0x8002bf83,
+ 0x2977c85e,
+ 0xd3b3d19a,
+ 0xa92bf132,
+ 0xa280efd8,
+ 0x83f7ad6e,
+ 0x748969c7,
+ 0x25ff411d,
+ 0x3854d3a8,
+ 0x55746aa2,
+ 0x00db5c54,
+ 0x36949e0d,
+ 0x40402ab6,
+ 0x1a720211,
+ 0xe02ce823,
+ 0x4ac104a2,
+ 0x214d2e4b,
+ 0x267e5c83,
+ 0x38a3a483,
+ 0xd1da1f67,
+ 0x0c68db2c,
+ 0xd7035d63,
+ 0xa29393bb,
+ 0xa5743519,
+ 0xcb97c84e,
+ 0xa853974f,
+ 0x147360a0,
+ 0x2df9b3f4,
+ 0x0aff129e,
+ 0x177d687f,
+ 0x87eff911,
+ 0x6c60b354,
+ 0x6c356c38,
+ 0x7d480965,
+ 0xbb06a193,
+ 0x25b0568e,
+ 0x6fd6da9a,
+ 0x82b64f14,
+ 0x3d267a78,
+ 0xf100b6a7,
+ 0x32c74539,
+ 0x6042e152,
+ 0x4548276e,
+ 0xa3a32b70,
+ 0xf029fe15,
+ 0xa9b8bd2f,
+ 0x5618eee4,
+ 0x9815a5f0,
+ 0x89fb2850,
+ 0xa9261b26,
+ 0xded9e505,
+ 0x37e9d749,
+ 0xdc4aeb78,
+ 0x9e634f7a,
+ 0xcf638d2d,
+ 0x6b679f92,
+ 0x2b64911d,
+ 0xe6d1312f,
+ 0x88b3e76a,
+ 0x56311f62,
+ 0x00916de7,
+ 0x39d0bc61,
+ 0x8ac09356,
+ 0x47abcfce,
+ 0x324cb73e,
+ 0xfadcd0a8,
+ 0x2f2fbca8,
+ 0x945eda22,
+ 0xba23cab1,
+ 0xf9fb4212,
+ 0x1fa71d45,
+ 0x867a034e,
+ 0x3bee5db1,
+ 0xf54adced,
+ 0x6633ba77,
+ 0xe1eb4f1e,
+ 0x97ef01f6,
+ 0x57fd3b32,
+ 0x5234d80d,
+ 0xe8ee95f3,
+ 0x5dc990bf,
+ 0xaba833e1,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c new file mode 100644 index 0000000000..7c13b8fd32 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -0,0 +1,236 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "X6DHR-iG "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_pxhd_3; + unsigned char bus_pxhd_4; + unsigned char bus_ich5r_1; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* ich5r */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1f.0, using defaults\n"); + + bus_ich5r_1 = 9; + bus_isa = 10; + } + /* pxhd-1 */ + dev = dev_find_slot(2, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n"); + + bus_pxhd_1 = 3; + } + /* pxhd-2 */ + dev = dev_find_slot(2, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_pxhd_2 = 4; + } + + /* pxhd-3 */ + dev = dev_find_slot(5, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n"); + + bus_pxhd_3 = 6; + } + /* pxhd-4 */ + dev = dev_find_slot(5, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_pxhd_4 = 7; + } + + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct resource *res; + device_t dev; + /* pxhd apic 3 */ + dev = dev_find_slot(2, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x03, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 2:00.1\n"); + } + /* pxhd apic 4 */ + dev = dev_find_slot(2, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x04, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 2:00.3\n"); + } + /* pxhd apic 5 */ + dev = dev_find_slot(5, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x05, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 5:00.1\n"); + } + /* pxhd apic 8 */ + dev = dev_find_slot(5, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x08, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 5:00.3\n"); + } + } + + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x76, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_2, 0x08, 0x04, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_2, 0x09, 0x04, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_3, 0x08, 0x05, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_4, 0x08, 0x08, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + (bus_isa - 1), 0x04, 0x02, 0x10); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/supermicro/x6dhr_ig/reset.c b/src/mainboard/supermicro/x6dhr_ig/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c new file mode 100644 index 0000000000..e9012a49f3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -0,0 +1,99 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ICH5_WDBASE 0x400 +#define ICH5_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ +#if 0 + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +#endif +} + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_jarell_frb3(void) +{ +#if 0 + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 0); + pci_write_config16(dev, 0x04, value); + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); + base = ICH5_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Configure GPIO 48 and 40 as GPIO */ + value = inl(base + 0x30); + value |= (1 << 16) | ( 1 << 8); + outl(value, base + 0x30); + + /* Configure GPIO 48 as Output */ + value = inl(base + 0x34); + value &= ~(1 << 16); + outl(value, base + 0x34); + + /* Toggle GPIO 48 high to low */ + value = inl(base + 0x38); + value |= (1 << 16); + outl(value, base + 0x38); + value &= ~(1 << 16); + outl(value, base + 0x38); +#endif +} + +static void disable_watchdogs(void) +{ +// disable_sio_watchdog(NSC_WD_DEV); + disable_ich5_watchdog(); +// disable_jarell_frb3(); + print_debug("Watchdogs disabled\r\n"); +} + diff --git a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c new file mode 100644 index 0000000000..82c070b0c1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c @@ -0,0 +1,23 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + return; +} + + + + diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb new file mode 100644 index 0000000000..dff583ce2c --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -0,0 +1,209 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 # mch + device pci_domain 0 on + chip southbridge/intel/ich5r # ich5r + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> Bridge + device pci 1e.0 on end + + # -> ISA + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + # -> IDE + device pci 1f.1 on end + # -> SATA + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 1 + device pci 0.0 on + # On board gig e1000 + chip drivers/generic/generic + device pci 03.0 on end + device pci 03.1 on end + end + end + device pci 0.1 on end + device pci 0.2 on end + device pci 0.3 on end + end + end + device pci 04.0 on end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070105" +end + diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb new file mode 100644 index 0000000000..8461cdb7d1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -0,0 +1,228 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DHR" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c new file mode 100644 index 0000000000..cd7c18111f --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c @@ -0,0 +1,169 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/ich5r/ich5r_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "x6dhr2_fixups.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D0F0 | \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0808090a +#define RECVENB_CONFIG 0x0808090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); + mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x00100000, 0x01000000); + ram_check(0x00100000, 0x00100100); + /* check the first 1M in the 3rd Gig */ +// ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/chip.h b/src/mainboard/supermicro/x6dhr_ig2/chip.h new file mode 100644 index 0000000000..016f20a3fd --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_supermicro_x6dhr_ig2_ops; + +struct mainboard_supermicro_x6dhr_ig2_config { + int nothing; +}; diff --git a/src/mainboard/supermicro/x6dhr_ig2/cmos.layout b/src/mainboard/supermicro/x6dhr_ig2/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/failover.c b/src/mainboard/supermicro/x6dhr_ig2/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c b/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c new file mode 100644 index 0000000000..5ed51feaa1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(15*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x24d0, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00}, + {0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00} + } +}; diff --git a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c new file mode 100644 index 0000000000..c1891a222b --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations mainboard_supermicro_x6dhr_ig2_ops = { + CHIP_NAME("Supermicro x6dhr-ig2") +}; + diff --git a/src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c b/src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c new file mode 100644 index 0000000000..b2e72ab616 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF3413.TXT - Noconoa D-0 */
+
+ 0x00000001, /* Header Version */
+ 0x00000013, /* Patch ID */
+ 0x07302004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x95f183f0, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb2abaca8,
+ 0x6b62b8e0,
+ 0x0af32c41,
+ 0x12ca6048,
+ 0x5bd55ae6,
+ 0xb90dfc1d,
+ 0x565fe2b2,
+ 0x326b1718,
+ 0x61f3a40d,
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+ 0x700f2003,
+ 0x501cbef7,
+ 0x4068b05e,
+ 0xa24c4580,
+ 0x4da75506,
+ 0x500b9b0f,
+ 0x22e3a600,
+ 0x7bec4e94,
+ 0x8f0958e2,
+ 0x42129a1e,
+ 0xb46d8dc5,
+ 0x29f8851c,
+ 0x83fb38bd,
+ 0x17b0de15,
+ 0x15340d20,
+ 0x74f00fde,
+ 0x6c646b32,
+ 0x905897c4,
+ 0x4d8ed991,
+ 0x3cf91fd5,
+ 0x0ee02ddf,
+ 0xec069ce6,
+ 0x0b977683,
+ 0xa0bf31f6,
+ 0xa1d135a9,
+ 0xa882d1db,
+ 0xa731a63a,
+ 0x48e211f1,
+ 0xf3d89e99,
+ 0xf982e6ea,
+ 0x23dde303,
+ 0x7f1ff8da,
+ 0xdc8c6414,
+ 0x806f432e,
+ 0xd047bc02,
+ 0x671bacff,
+ 0xd40ba2a8,
+ 0xe3666685,
+ 0x31265f9f,
+ 0x3931a952,
+ 0x62f35606,
+ 0xc48f0c5e,
+ 0xfd107640,
+ 0xf636da24,
+ 0xb8f5c3b0,
+ 0x1c91e88f,
+ 0xed9dd432,
+ 0x2b85fa5d,
+ 0x8b15d2ac,
+ 0x1e06cf24,
+ 0x1def6e9c,
+ 0xfae9175f,
+ 0x03ac6f02,
+ 0x37318c87,
+ 0xbc0b1ce5,
+ 0xa0640cab,
+ 0x6cc20a3c,
+ 0x1c7b2524,
+ 0x4685dacc,
+ 0xeab8bb31,
+ 0x8063b5d0,
+ 0x79817d52,
+ 0x211b1972,
+ 0xd7bfc987,
+ 0xab9128dc,
+ 0x150d9b36,
+ 0x6a5838ab,
+ 0x9a0a304d,
+ 0x2e43c331,
+ 0x84f2c4b8,
+ 0x435146c1,
+ 0xed64a280,
+ 0x553ecb4c,
+ 0x5c800db2,
+ 0xeef4df95,
+ 0x5dcf2c37,
+ 0x70755ddf,
+ 0x4274737b,
+ 0xe610350e,
+ 0xd97a5997,
+ 0x7af5edce,
+ 0xfd18ba0c,
+ 0xb7587cd8,
+ 0xfa5e42d6,
+ 0x76bde9eb,
+ 0xec41eead,
+ 0x604d2423,
+ 0xb4adbcf9,
+ 0xce728fa3,
+ 0x02361c31,
+ 0x02fab64d,
+ 0x00316b1c,
+ 0x562f9aa4,
+ 0x71f85790,
+ 0x9cb6d464,
+ 0x32949ebf,
+ 0x434fc23d,
+ 0xee7fac51,
+ 0xda5cc63a,
+ 0x17e616b4,
+ 0xcd1bd1bc,
+ 0x14638cae,
+ 0xd31808fa,
+ 0xb16e0727,
+ 0xfdda2b0f,
+ 0xbc11c678,
+ 0xfe79dc6e,
+ 0xe26eefb4,
+ 0x9a78de16,
+ 0xb68f2df2,
+ 0xd47da234,
+ 0xbdff28a4,
+ 0x937bb1f4,
+ 0x0786dd46,
+ 0xbd1160f5,
+ 0xf77b070c,
+ 0x72b7c51e,
+ 0xcbb3a371,
+ 0x5e50e904,
+ 0x00fbc379,
+ 0x680757dd,
+ 0xd38193f7,
+ 0x93113e25,
+ 0x7b258da7,
+ 0x991aaa09,
+ 0xab1415be,
+ 0xa3740774,
+ 0x370b72e5,
+ 0x2fc643f4,
+ 0x3916d70e,
+ 0xea2838d3,
+ 0xe4840c42,
+ 0xd18e6959,
+ 0x69a270ee,
+ 0xee4a494e,
+ 0x0329799b,
+ 0x07480357,
+ 0x0260c46f,
+ 0x7b75346e,
+ 0x787234f4,
+ 0xe0adf25b,
+ 0xba85cacf,
+ 0xb5724eb1,
+ 0xfde2c080,
+ 0x2b6bb492,
+ 0xd2f70545,
+ 0x9ca97510,
+ 0x4034c18f,
+ 0x616bcb12,
+ 0x5667f52a,
+ 0xe2f6bfce,
+ 0x1f25969e,
+ 0x569eaab7,
+ 0x27ad8196,
+ 0x2d30a6d0,
+ 0x96d6c10a,
+ 0xcb9f024f,
+ 0x3d7941ef,
+ 0xf7a76bc5,
+ 0xe9a701d4,
+ 0xd53293a3,
+ 0x252cf5df,
+ 0xaf9172f6,
+ 0xd090c809,
+ 0xb1a17387,
+ 0x045a0987,
+ 0x92d9ffd9,
+ 0xb30c449c,
+ 0x2180ff58,
+ 0x2929f7de,
+ 0x3f91766e,
+ 0x9f488e3d,
+ 0x05dd6734,
+ 0x82482f5b,
+ 0x01da3ca2,
+ 0x42f33408,
+ 0xf8e3ba89,
+ 0x750ac2ff,
+ 0x39f11551,
+ 0x71087971,
+ 0x368fa634,
+ 0xefda0572,
+ 0x14b8f750,
+ 0xe5768705,
+ 0x71c168e2,
+ 0x8c012c63,
+ 0x12ad74ce,
+ 0x841c17ea,
+ 0xe6f44176,
+ 0x36cf2557,
+ 0x14760a6d,
+ 0x4bb3b7c2,
+ 0x14d1437d,
+ 0xbe673210,
+ 0x4d6ba9f5,
+ 0xe68abbf9,
+ 0xc311908d,
+ 0x46b63956,
+ 0xac2c9fb3,
+ 0xab769ce8,
+ 0xa29d7040,
+ 0xec3d67e3,
+ 0xdef311de,
+ 0x52a53b14,
+ 0xca924769,
+ 0xf35d1514,
+ 0x524b0471,
+ 0xc0d08591,
+ 0x454fc34c,
+ 0xca719639,
+ 0x9af2f230,
+ 0xa023a821,
+ 0x3d6539ba,
+ 0x90d0d7a2,
+ 0xc65fc56e,
+ 0x4eb2aa19,
+ 0xeba3b0e7,
+ 0x1bb5b33e,
+ 0xab8c68c2,
+ 0x0f1793d3,
+ 0xdcf176e9,
+ 0x1b7bbba0,
+ 0x96170a27,
+ 0x1955452d,
+ 0x42e88c71,
+ 0x48cad4b3,
+ 0xdcc36042,
+ 0x90619951,
+ 0x7566bc7c,
+ 0xe14ba224,
+ 0xc24ad73d,
+ 0xdb04144d,
+ 0xd9792727,
+ 0x11150943,
+ 0xe45f0c57,
+ 0xb87d184e,
+ 0x3cf13243,
+ 0x2010d95c,
+ 0x84c347c1,
+ 0x6d0f2461,
+ 0xb5c41194,
+ 0xde7ccb2e,
+ 0xb929ecb0,
+ 0x51fbd8f7,
+ 0x45dc65fb,
+ 0x6902d2c0,
+ 0xb940814f,
+ 0xf339e083,
+ 0x6f370d56,
+ 0xcaf5638e,
+ 0xe8a3cb83,
+ 0xacf414b6,
+ 0xe61095a1,
+ 0x99b4cde4,
+ 0x55112fed,
+ 0x606b9d53,
+ 0x5a05974a,
+ 0xa4c7db34,
+ 0xdc92469b,
+ 0xf9280621,
+ 0xe7b1ef95,
+ 0xc0fc5be8,
+ 0x74a1da09,
+ 0xa92a4b7f,
+ 0x3d65d75e,
+ 0xe3804335,
+ 0x1ff49e19,
+ 0x71da8170,
+ 0xac69069b,
+ 0x04aae3d5,
+ 0xc0ef4b46,
+ 0x091a3482,
+ 0x8356c7ae,
+ 0x32ecb208,
+ 0x900c89ed,
+ 0x2a206ff5,
+ 0x7eed5032,
+ 0x5b55b25d,
+ 0xf98d6df2,
+ 0xf52bc8a9,
+ 0x1aa2f5fe,
+ 0x1d33c0bf,
+ 0x3cd34e89,
+ 0x9a0da4ae,
+ 0x1c205917,
+ 0x7ca784cd,
+ 0xf7dda662,
+ 0xad97f3ff,
+ 0x525c53ec,
+ 0x024f11ff,
+ 0x32c3ae5b,
+ 0xbf372800,
+ 0x8ff15f4d,
+ 0x7605d019,
+ 0x0dae7740,
+ 0x5f5dd0ef,
+ 0x0f6c37d0,
+ 0xee6fa91e,
+ 0xb9f51051,
+ 0x39a9f0d1,
+ 0x22bf03fb,
+ 0x485a0922,
+ 0x7384b30e,
+ 0x85ba7f16,
+ 0xb1f0a524,
+ 0x7e9c5113,
+ 0x240d9306,
+ 0x1ca7b0ea,
+ 0x18a0d114,
+ 0x76b64213,
+ 0x31212cc0,
+ 0xc9dca5c3,
+ 0x69f2ae52,
+ 0x545caa7c,
+ 0xfb2ff045,
+ 0x3f3a1af5,
+ 0xe75b6913,
+ 0x775a1c79,
+ 0x4627e25f,
+ 0x90a14b97,
+ 0x06456383,
+ 0x3d52cf69,
+ 0xfb2492c3,
+ 0x39f25a22,
+ 0x81f68c55,
+ 0x87b14e15,
+ 0x0920af5d,
+ 0xe2585678,
+ 0x0671e46d,
+ 0xb77ddb67,
+ 0x3948c4b3,
+ 0x122dddef,
+ 0xd0726172,
+ 0xd3302234,
+ 0x58bab4e4,
+ 0x195ac247,
+ 0x082459f0,
+ 0x18a2566d,
+ 0xbf56078d,
+ 0x116ed409,
+ 0x5ccc0f80,
+ 0xbae0b4ca,
+ 0x21a6325d,
+ 0x7e1f0c40,
+ 0x595326d4,
+ 0x518b2244,
+ 0x8ab3cdb7,
+ 0xbe6b4835,
+ 0xfc39f8ac,
+ 0x63b167aa,
+ 0x194f070d,
+ 0xed3d0416,
+ 0xae16758a,
+ 0xb9bb6bbf,
+ 0x477d9c85,
+ 0x9808c304,
+ 0xe1d8cec4,
+ 0x7ee22e17,
+ 0x0a7a9d7f,
+ 0xcc98173a,
+ 0x5f78dc21,
+ 0x364bc95e,
+ 0xb54608d9,
+ 0x5d4d70ea,
+ 0x083a7f79,
+ 0x59ffbd73,
+ 0x4f3e9eaf,
+ 0x68755ad4,
+ 0xab254689,
+ 0x11bf09a8,
+ 0xbbc40098,
+ 0x969ca3eb,
+ 0x30eee9d2,
+ 0xe35bc37e,
+ 0xcb2d678f,
+ 0x7846876b,
+ 0xf0d28ae7,
+ 0xc092fbb2,
+ 0x321b344a,
+ 0xcc5ee81b,
+ 0xd2afa00f,
+ 0xfeccd86a,
+ 0x6e5e55c2,
+ 0x2b5543ea,
+ 0x810e4009,
+ 0xea2d8e20,
+ 0x6acae3b9,
+ 0x3828e15e,
+ 0xe1e4821c,
+ 0xf429da70,
+ 0x35f6565c,
+ 0x64b1baa8,
+ 0x350e9583,
+ 0xd2522d4f,
+ 0x5e28a3f1,
+ 0x949ff0aa,
+ 0x3c1b5694,
+ 0x146dde1f,
+ 0x6f3430e1,
+ 0x71c077b7,
+ 0x4d145924,
+ 0xe431cd28,
+ 0xb315cfde,
+ 0xa0365a4a,
+ 0x473de1aa,
+ 0xcbe4e999,
+ 0x319906e9,
+ 0xad0fea9c,
+ 0x89e4e72d,
+ 0x9dbba94d,
+ 0xd395c1c5,
+ 0xa1fff11a,
+ 0x8447e120,
+ 0xe5c59100,
+ 0xa07cb778,
+ 0x8f30a039,
+ 0xed78facb,
+ 0x86de9373,
+ 0x550c4889,
+ 0xce71e3a8,
+ 0x06167b3a,
+ 0x5abdd9a3,
+ 0xc8a9e48d,
+ 0xe3312905,
+ 0x7a63a146,
+ 0xc0f19763,
+ 0xda0cf9db,
+ 0x1d708306,
+ 0x0e41f0ba,
+ 0x4c7939fe,
+ 0x768e48c2,
+ 0xe925fd31,
+ 0x309e7870,
+ 0xfc261b87,
+ 0xc897b2de,
+ 0x6c714792,
+ 0x41c7fbac,
+ 0x57d0b3c3,
+ 0x4fa82a55,
+ 0xd56b4a87,
+ 0x81e5cabc,
+ 0xb260cb7b,
+ 0x520927ab,
+ 0x20d0ab46,
+ 0xc9f92ddf,
+ 0x81f4a21d,
+ 0xfc5a0ca2,
+ 0x95d16aad,
+ 0xe54d7847,
+ 0x6080cc07,
+ 0x0df73f7e,
+ 0xaa8d5187,
+ 0x97a0bc12,
+ 0xb22c5e68,
+ 0x0954d7dc,
+ 0x3368ab5a,
+ 0xd12541df,
+ 0x58119260,
+ 0xe5b0e1df,
+ 0x25027fa4,
+ 0x5780425d,
+ 0x29bb8791,
+ 0x4100b7a9,
+ 0x076b3519,
+ 0x15e0ebb4,
+ 0xe5fb9273,
+ 0x6dbf07e7,
+ 0x1f82bddd,
+ 0x03691b6b,
+ 0xbacef28c,
+ 0x9909ed5a,
+ 0x98886793,
+ 0x544f9a82,
+ 0x9d9749d0,
+ 0x38441606,
+ 0xc4a9f4d2,
+ 0x6ce2bcf1,
+ 0x1c7c3abd,
+ 0x62c621f1,
+ 0x871ee1e4,
+ 0xa83930ce,
+ 0xbe1ee459,
+ 0xd61f1ca4,
+ 0x8c4450e5,
+ 0x98031ca9,
+ 0xe52f54e2,
+ 0xd0c4c737,
+ 0x76074160,
+ 0xbf050c3b,
+ 0x2603af14,
+ 0x43cbb0bc,
+ 0xc631b9e8,
+ 0x26030719,
+ 0x993f570c,
+ 0xdda34038,
+ 0xe34a9793,
+ 0x337a124c,
+ 0x2aa8af16,
+ 0xf80d7473,
+ 0xf01d9397,
+ 0x68e1afb9,
+ 0x0eb37ad2,
+ 0xf71969f9,
+ 0xdf020552,
+ 0x75aa9b30,
+ 0xffa210cf,
+ 0x543c414f,
+ 0xa1e3faec,
+ 0x40891d7e,
+ 0x6b48a6c5,
+ 0xec09a1a0,
+ 0x97a31f2a,
+ 0x5a6be2d7,
+ 0xd06e492b,
+ 0xc54290af,
+ 0xcb524021,
+ 0x420e8c4d,
+ 0xfb135c17,
+ 0x2bfc8adb,
+ 0x9f0cfb46,
+ 0x564db712,
+ 0x7a97a227,
+ 0x8bb98daf,
+ 0xdd0d6180,
+ 0x3d28b9e3,
+ 0xe505050f,
+ 0x19a9868e,
+ 0x7bf5685f,
+ 0x35d698c4,
+ 0xce7e1de3,
+ 0x360a64af,
+ 0x25a1f022,
+ 0xe26c1d04,
+ 0x5b3fb364,
+ 0x932f25f7,
+ 0x9a2aa00d,
+ 0xc50fb773,
+ 0xec45ea3a,
+ 0x22ddf8e4,
+ 0xafb6a6c8,
+ 0x876d04f7,
+ 0xd9c86c3c,
+ 0xd54bee2d,
+ 0xf4e28199,
+ 0xc3456776,
+ 0x04c3107b,
+ 0xbf914e9d,
+ 0x23fefaa5,
+ 0x0931a133,
+ 0x41467758,
+ 0x8ec49707,
+ 0x5ed48709,
+ 0xd11c2de8,
+ 0xb687a0b9,
+ 0xdc908383,
+ 0xd8037ff3,
+ 0xd4311a9f,
+ 0xd00aeb6a,
+ 0xfe54df3b,
+ 0x9c51ce4d,
+ 0x36956408,
+ 0xcd28ef09,
+ 0xc68932b0,
+ 0x7c31e782,
+ 0x28b4723c,
+ 0xededacc2,
+ 0x6ddbac6b,
+ 0x775a7fc1,
+ 0x6909906f,
+ 0xa774123c,
+ 0xf63145ad,
+ 0x287b191e,
+ 0x59d79300,
+ 0xbf76a2fc,
+ 0xfbaf9207,
+ 0x2fe5b7f6,
+ 0xebe7c103,
+ 0x71ac0a8d,
+ 0x2028c3c7,
+ 0xd2cb4917,
+ 0xd74a4ee4,
+ 0xfce405d8,
+ 0xad83fd0f,
+ 0x8f9ec3da,
+ 0xaab2301c,
+ 0xc6f1339f,
+ 0xc652bced,
+ 0xe378b272,
+ 0x18e1ff34,
+ 0x9ec778b6,
+ 0xce1a3883,
+ 0x7c5e5eaf,
+ 0xd16ec37a,
+ 0xa69e45f4,
+ 0xc36cd4aa,
+ 0x045b391f,
+ 0x5a2a08f1,
+ 0x4dd8d53e,
+ 0xd64796ec,
+ 0x4476fc28,
+ 0x18dbaa50,
+ 0x00fb2407,
+ 0x177db915,
+ 0x5969758b,
+ 0x3030964a,
+ 0x81d6485b,
+ 0x7d2e12b0,
+ 0x624d6c5f,
+ 0x0746bbc0,
+ 0xe669d150,
+ 0x0465eef7,
+ 0x09764011,
+ 0x551995e4,
+ 0x8422dedf,
+ 0x0ca56194,
+ 0x293eab2e,
+ 0xf20a137a,
+ 0x55117fc2,
+ 0xbc5431af,
+ 0x064751fa,
+ 0xc0dafdb2,
+ 0x6c3b1d4f,
+ 0xeac335b3,
+ 0x71173afc,
+ 0x31c84b7c,
+ 0xfef2b4ab,
+ 0x59ca5fa2,
+ 0x664c8b4e,
+ 0x7dfd560b,
+ 0xdb0daff3,
+ 0x51f87bfa,
+ 0x58015d2e,
+ 0x67a827b4,
+ 0x62cebc1a,
+ 0x24b37298,
+ 0x75b589be,
+ 0x874f1800,
+ 0x277b795c,
+ 0xf762489e,
+ 0x87d00752,
+ 0x9be45ed1,
+ 0x296ec120,
+ 0x61162480,
+ 0x792e8a2c,
+ 0x3b631590,
+ 0xe33ba0cf,
+ 0x542ac23c,
+ 0xe1e8cffa,
+ 0xfc084cd8,
+ 0xc115ad31,
+ 0x71559928,
+ 0x791f1e33,
+ 0x662ed92b,
+ 0x7222c76d,
+ 0x02dcd566,
+ 0x8db9b4d4,
+ 0xa5f344c8,
+ 0x15806b12,
+ 0x81e572f7,
+ 0x3b3fbe25,
+ 0x2133b413,
+ 0x2d68a367,
+ 0x356f6ce7,
+ 0xcd6dfed1,
+ 0xd8b3a26e,
+ 0xe9d328da,
+ 0x127425ab,
+ 0x83a60aac,
+ 0x8cc26190,
+ 0x7f87ab26,
+ 0x56faab5f,
+ 0x76d0feaa,
+ 0x4b25dd10,
+ 0x4f6286ea,
+ 0x79298d06,
+ 0x8002bf83,
+ 0x2977c85e,
+ 0xd3b3d19a,
+ 0xa92bf132,
+ 0xa280efd8,
+ 0x83f7ad6e,
+ 0x748969c7,
+ 0x25ff411d,
+ 0x3854d3a8,
+ 0x55746aa2,
+ 0x00db5c54,
+ 0x36949e0d,
+ 0x40402ab6,
+ 0x1a720211,
+ 0xe02ce823,
+ 0x4ac104a2,
+ 0x214d2e4b,
+ 0x267e5c83,
+ 0x38a3a483,
+ 0xd1da1f67,
+ 0x0c68db2c,
+ 0xd7035d63,
+ 0xa29393bb,
+ 0xa5743519,
+ 0xcb97c84e,
+ 0xa853974f,
+ 0x147360a0,
+ 0x2df9b3f4,
+ 0x0aff129e,
+ 0x177d687f,
+ 0x87eff911,
+ 0x6c60b354,
+ 0x6c356c38,
+ 0x7d480965,
+ 0xbb06a193,
+ 0x25b0568e,
+ 0x6fd6da9a,
+ 0x82b64f14,
+ 0x3d267a78,
+ 0xf100b6a7,
+ 0x32c74539,
+ 0x6042e152,
+ 0x4548276e,
+ 0xa3a32b70,
+ 0xf029fe15,
+ 0xa9b8bd2f,
+ 0x5618eee4,
+ 0x9815a5f0,
+ 0x89fb2850,
+ 0xa9261b26,
+ 0xded9e505,
+ 0x37e9d749,
+ 0xdc4aeb78,
+ 0x9e634f7a,
+ 0xcf638d2d,
+ 0x6b679f92,
+ 0x2b64911d,
+ 0xe6d1312f,
+ 0x88b3e76a,
+ 0x56311f62,
+ 0x00916de7,
+ 0x39d0bc61,
+ 0x8ac09356,
+ 0x47abcfce,
+ 0x324cb73e,
+ 0xfadcd0a8,
+ 0x2f2fbca8,
+ 0x945eda22,
+ 0xba23cab1,
+ 0xf9fb4212,
+ 0x1fa71d45,
+ 0x867a034e,
+ 0x3bee5db1,
+ 0xf54adced,
+ 0x6633ba77,
+ 0xe1eb4f1e,
+ 0x97ef01f6,
+ 0x57fd3b32,
+ 0x5234d80d,
+ 0xe8ee95f3,
+ 0x5dc990bf,
+ 0xaba833e1,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c new file mode 100644 index 0000000000..61ece13f5a --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -0,0 +1,219 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "X6DHR-iG "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_pxhd_3; + unsigned char bus_pxhd_4; + unsigned char bus_ich5r_1; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* ich5r */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + + bus_ich5r_1 = 7; + bus_isa = 8; + } + /* pxhd-1 */ + dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.0, using defaults\n"); + + bus_pxhd_1 = 2; + } + /* pxhd-2 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.2, using defaults\n"); + + bus_pxhd_2 = 3; + } + + /* pxhd-3 */ + dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); + if (dev) { + bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:04.0, using defaults\n"); + + bus_pxhd_3 = 5; + } + /* pxhd-4 */ + dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); + if (dev) { + bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:06.0, using defaults\n"); + + bus_pxhd_4 = 6; + } + + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct resource *res; + device_t dev; + /* pxhd apic 3 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x03, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); + } + /* pxhd apic 4 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x04, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); + } + } + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x76, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x08, 0x03, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x0c, 0x03, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x0d, 0x03, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_2, 0x08, 0x04, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_ich5r_1, 0x04, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_4, 0x00, 0x02, 0x10); +#if 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + (bus_isa - 1), 0x04, 0x02, 0x10); +#endif + /* Standard local interrupt assignments */ +#if 0 + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x00); +#endif + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/supermicro/x6dhr_ig2/reset.c b/src/mainboard/supermicro/x6dhr_ig2/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c new file mode 100644 index 0000000000..e9012a49f3 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -0,0 +1,99 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ICH5_WDBASE 0x400 +#define ICH5_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ +#if 0 + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +#endif +} + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + +static void disable_jarell_frb3(void) +{ +#if 0 + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 0); + pci_write_config16(dev, 0x04, value); + + /* Set gpio base */ + pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); + base = ICH5_GPIOBASE; + + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value); + + /* Configure GPIO 48 and 40 as GPIO */ + value = inl(base + 0x30); + value |= (1 << 16) | ( 1 << 8); + outl(value, base + 0x30); + + /* Configure GPIO 48 as Output */ + value = inl(base + 0x34); + value &= ~(1 << 16); + outl(value, base + 0x34); + + /* Toggle GPIO 48 high to low */ + value = inl(base + 0x38); + value |= (1 << 16); + outl(value, base + 0x38); + value &= ~(1 << 16); + outl(value, base + 0x38); +#endif +} + +static void disable_watchdogs(void) +{ +// disable_sio_watchdog(NSC_WD_DEV); + disable_ich5_watchdog(); +// disable_jarell_frb3(); + print_debug("Watchdogs disabled\r\n"); +} + diff --git a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c new file mode 100644 index 0000000000..82c070b0c1 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c @@ -0,0 +1,23 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + return; +} + + + + diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index 568bc9b211..3977db16b9 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index 16b23a66bd..ada1beb593 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,21 +89,16 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - ## Delay timer options ## default CONFIG_UDELAY_TSC=1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - ## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table @@ -148,8 +140,8 @@ default SERIAL_CPU_INIT=0 ## enable CACHE_AS_RAM specifics ## default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xF2000000 -#default DCACHE_RAM_BASE=0xcf000 +#default DCACHE_RAM_BASE=0xF2000000 +default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 #default CONFIG_USE_INIT=1 diff --git a/src/mainboard/tyan/s2735/reset.c b/src/mainboard/tyan/s2735/reset.c new file mode 100644 index 0000000000..3cc3d54988 --- /dev/null +++ b/src/mainboard/tyan/s2735/reset.c @@ -0,0 +1,5 @@ + +void hard_reset(void) +{ + i82801er_hard_reset(); +} diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 89de7dba33..df8788233b 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -39,9 +39,33 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else ## ## Romcc output @@ -65,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -84,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -93,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -110,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -117,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2850 diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index c9b56b2811..646293e20e 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -45,9 +42,9 @@ uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -57,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -84,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=2 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -119,20 +112,29 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=1 +default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=0 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 -#BTEXT CONSOLE -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA +#VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 + ## ## Build code to setup a generic IOAPIC ## @@ -141,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2850" +default MAINBOARD_PART_NUMBER="S2850" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 @@ -231,9 +233,9 @@ default TTYS0_LCS=0x3 ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=7 +default DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=7 +default MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c index 9220738d87..0b9012aca8 100644 --- a/src/mainboard/tyan/s2850/auto.c +++ b/src/mainboard/tyan/s2850/auto.c @@ -25,21 +25,52 @@ #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} static void hard_reset(void) { - set_bios_reset(); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + + set_bios_reset(); - /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); + /* enable cf9 */ + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); } #define REV_B_RESET 0 diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 6a28ecbe79..fe175795e2 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +52,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned apicid_base; unsigned apicid_8111; @@ -41,8 +78,14 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -89,7 +132,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (2<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13); //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2850/reset.c b/src/mainboard/tyan/s2850/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2850/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index f042467f5c..bd61fcb34f 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -39,11 +39,34 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + ## ## Romcc output ## @@ -66,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -85,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -94,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -111,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -118,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2875 diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb index 5851318be6..a584d1b436 100644 --- a/src/mainboard/tyan/s2875/Options.lb +++ b/src/mainboard/tyan/s2875/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -47,6 +44,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -56,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -83,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=5 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -118,16 +112,28 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=0 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 #VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s2875/auto.c b/src/mainboard/tyan/s2875/auto.c index 1b055bf2ec..7b75db20ab 100644 --- a/src/mainboard/tyan/s2875/auto.c +++ b/src/mainboard/tyan/s2875/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -141,6 +173,7 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else nodeid = lapicid(); @@ -155,7 +188,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 9b93decd80..394410b5ba 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -7,6 +7,40 @@ #include <cpu/amd/dualcore.h> #endif +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +50,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned char bus_8151_1; unsigned apicid_base; @@ -43,8 +78,15 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x04,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -58,7 +100,7 @@ void *smp_write_config_table(void *v) bus_isa = 4; } /* 8151 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); printk_debug("bus_8151_1=%d\n",bus_8151_1); @@ -105,9 +147,9 @@ void *smp_write_config_table(void *v) //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio ??? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2875/reset.c b/src/mainboard/tyan/s2875/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2875/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 6c4ac7b7c1..f7ad508347 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -39,10 +39,33 @@ arch i386 end ## driver mainboard.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end +end +else ## ## Romcc output @@ -66,13 +89,22 @@ makerule ./auto.inc action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end ## ## Build our reset vector (This is where linuxBIOS is entered) @@ -85,8 +117,11 @@ else ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -94,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end end ### @@ -111,6 +157,19 @@ end ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -118,11 +177,13 @@ mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end + ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME - config chip.h + config chip.h end # sample config for tyan/s2880 diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb index a6b4e86f50..1f929b0edc 100644 --- a/src/mainboard/tyan/s2880/Options.lb +++ b/src/mainboard/tyan/s2880/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -47,6 +44,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC @@ -56,6 +54,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_E0_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -83,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -122,6 +116,9 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + #1G memory hole default K8_E0_MEM_HOLE_SIZEK=0x100000 @@ -129,6 +126,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000 default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 + ## ## Build code to setup a generic IOAPIC ## @@ -137,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2880" +default MAINBOARD_PART_NUMBER="S2880" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c index 1ed43bc19e..2532386132 100644 --- a/src/mainboard/tyan/s2880/auto.c +++ b/src/mainboard/tyan/s2880/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -155,7 +187,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -179,8 +211,4 @@ static void main(unsigned long bist) soft_reset(); } - enable_smbus(); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - } diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index 4ffc5cffa0..08c51795fd 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr); + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 9c4764a77b..d013a463fa 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +52,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -45,9 +82,16 @@ void *smp_write_config_table(void *v) { device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -60,7 +104,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -71,7 +115,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -105,14 +149,14 @@ void *smp_write_config_table(void *v) device_t dev; struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } - dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -137,7 +181,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); //On Board AMD USB diff --git a/src/mainboard/tyan/s2880/reset.c b/src/mainboard/tyan/s2880/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2880/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 2e564ce9ea..02c6ec8255 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -44,8 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -67,6 +66,7 @@ end end else + ## ## Romcc output ## diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb index 84fa34e568..38eb3be4ef 100644 --- a/src/mainboard/tyan/s2881/Options.lb +++ b/src/mainboard/tyan/s2881/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s2881/auto.c b/src/mainboard/tyan/s2881/auto.c index 391be78879..fc622793d3 100644 --- a/src/mainboard/tyan/s2881/auto.c +++ b/src/mainboard/tyan/s2881/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -155,7 +187,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 5ac861d5da..bb037a4f61 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -13,6 +13,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" + #include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -37,20 +38,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -93,6 +126,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -136,7 +171,6 @@ void amd64_main(unsigned long bist) } /* Is this a secondary cpu? */ -// post_code(0x21); if (!boot_cpu()) { if (last_boot_normal()) { goto normal_image; @@ -154,7 +188,6 @@ void amd64_main(unsigned long bist) amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ -// post_code(0x22); if (bios_reset_detected() && last_boot_normal()) { goto normal_image; } @@ -166,13 +199,11 @@ void amd64_main(unsigned long bist) goto fallback_image; } normal_image: -// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist) /* inputs */ ); cpu_reset: -// post_code(0x24); #if 0 //CPU reset will reset memtroller ??? asm volatile ("jmp __cpu_reset" @@ -182,7 +213,6 @@ void amd64_main(unsigned long bist) #endif fallback_image: -// post_code(0x25); real_main(bist); } void real_main(unsigned long bist) @@ -275,17 +305,13 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2881_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -294,20 +320,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -324,6 +340,8 @@ void amd64_main(unsigned long bist) } #endif +#if 1 + cpu_reset_x: @@ -386,6 +404,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 06f1301ee5..ee92919db8 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -16,6 +51,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -46,9 +82,16 @@ void *smp_write_config_table(void *v) { device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 2); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -61,7 +104,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -72,7 +115,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -106,14 +149,14 @@ void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } - dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -138,7 +181,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //8111 LPC ???? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); //On Board AMD USB ??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2881/reset.c b/src/mainboard/tyan/s2881/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s2881/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 7739a67ca6..6f71a49864 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -44,7 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM @@ -278,36 +278,37 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end + device pci 1.3 on end + device pci 1.3 on +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end end # acpi device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0 diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb index 1249719210..ffa34c4f08 100644 --- a/src/mainboard/tyan/s2882/Options.lb +++ b/src/mainboard/tyan/s2882/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -153,7 +143,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2882" +default MAINBOARD_PART_NUMBER="S2882" default MAINBOARD_VENDOR="Tyan" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c index fb7a63abb5..910db9e8a5 100644 --- a/src/mainboard/tyan/s2882/auto.c +++ b/src/mainboard/tyan/s2882/auto.c @@ -27,20 +27,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); - + /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } #define REV_B_RESET 0 @@ -64,7 +96,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -160,7 +191,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -176,7 +207,6 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 start_other_cores(); #endif - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\r\n"); diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index 1b3d77a206..f0adb4204b 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -36,21 +36,52 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -93,6 +124,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -236,6 +269,7 @@ void amd64_main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 if(id.coreid == 0) { if (cpu_init_detected(id.nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } @@ -249,7 +283,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -261,7 +294,6 @@ void amd64_main(unsigned long bist) } } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -270,14 +302,11 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_default_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -288,21 +317,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -319,6 +337,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -382,6 +401,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index cdff230a2f..add22b4e03 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -1,301 +1,48 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> #include <arch/pirq_routing.h> +#include <device/pci.h> -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*15, /* there can be total 15 devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu -re (including checksum) */ - { - {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, - {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, - {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, - {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, - {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, - {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, - {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, - {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0}, - {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0}, - {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0}, - } -}; - -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - device_t dev; - unsigned reg; +#define IRQ_ROUTER_BUS 1 +#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) +#define IRQ_ROUTER_VENDOR 0x1022 +#define IRQ_ROUTER_DEVICE 0x746b - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; -#if 0 - printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); -#endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; -} +#define AVAILABLE_IRQS 0xdef8 +#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ + { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \ + {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +/* Each IRQ_SLOT entry consists of: + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + */ +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ + IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + IRQ_ROUTER_VENDOR, /* Vendor */ + IRQ_ROUTER_DEVICE, /* Device */ + 0x00, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb0, /* u8 checksum , mod 256 checksum must give zero */ + { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ + /* PCI Slot 1-6 */ + IRQ_SLOT(1, 3,1,0, 2,3,4,1 ), + IRQ_SLOT(2, 3,2,0, 3,4,1,2 ), + IRQ_SLOT(3, 2,1,0, 2,3,4,1 ), + IRQ_SLOT(4, 2,2,0, 3,4,1,2 ), + IRQ_SLOT(5, 4,5,0, 2,3,4,1 ), + IRQ_SLOT(6, 4,4,0, 1,2,3,4 ), + /* Onboard NICs */ + IRQ_SLOT(0, 2,3,0, 4,0,0,0 ), + IRQ_SLOT(0, 2,4,0, 4,0,0,0 ), + /* Let Linux know about bus 1 */ + IRQ_SLOT(0, 1,4,3, 0,0,0,0 ), + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - - uint8_t sum=0; - int i; - - unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); - - pirq = (void *)(addr); - v = (uint8_t *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = bus_chain_0; - pirq->rtr_devfn = (4<<3)|3; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1022; - pirq->rtr_device = 0x746b; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *) ( &pirq->checksum + 1); - slot_num = 0; - - { - device_t dev; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ5 - PINTB = IRQ9 - PINTC = IRQ11 - PINTD = IRQ10 - */ - pci_write_config16(dev, 0x56, 0xab95); - } - } - - printk_info("setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); - write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; - pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard ATI Display Adapter\n"); - static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6); - write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 1\n"); - static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3); - write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 2\n"); - static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 }; - pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1); - write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 3\n"); - static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 }; - pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3); - write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 4\n"); - static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 }; - pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2); - write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0); - pirq_info++; slot_num++; - - printk_info("setting Slot 5 \n"); - static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); - write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard SI Serail ATA\n"); - static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5); - write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard Intel NIC\n"); - static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8); - write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; - - printk_info("setting Onboard Adaptec SCSI\n"); - static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6); - write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; -#if 0 - //?? - write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0); - pirq_info++; slot_num++; -#endif - - printk_info("setting Onboard Broadcom NIC\n"); - static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9); - write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; -#if 0 - //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0); - pirq_info++; slot_num++; -#endif - -#if 0 - //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); - pirq_info++; slot_num++; -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - return (unsigned long) pirq_info; - + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2882/reset.c b/src/mainboard/tyan/s2882/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/tyan/s2882/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index a29c713ac6..f6ea627f8b 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -44,7 +44,7 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM @@ -66,7 +66,7 @@ end end else - + ## ## Romcc output ## diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 7bc324e606..79d60a3e3b 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index cff103b9cc..8275f6d5d7 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -26,20 +26,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { - set_bios_reset(); + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -192,7 +224,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -223,4 +255,5 @@ static void main(unsigned long bist) sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + } diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 3d27071031..85d4da9227 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -13,7 +13,6 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -38,20 +37,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -103,6 +134,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -159,6 +192,7 @@ void amd64_main(unsigned long bist) enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ @@ -296,15 +330,10 @@ void amd64_main(unsigned long bist) uart_init(); console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2885_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); @@ -319,17 +348,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 2396ade53e..a9683d577c 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -7,6 +7,42 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -51,9 +87,14 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_8151_0 = node_link_to_bus(0, 0); + if (bus_8151_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_8151_0 = 1; + } /* 8151 */ - bus_8151_0 = 1; - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); // printk_debug("bus_8151_1=%d\n",bus_8151_1); diff --git a/src/mainboard/tyan/s2885/reset.c b/src/mainboard/tyan/s2885/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s2885/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 53a7fee36e..6341926115 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -346,12 +346,13 @@ chip northbridge/amd/amdk8/root_complex end # pci_domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all +# device pnp 0.1 off end # pci_regs_all # device pnp 0.2 off end # mem # device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.4 off end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc +# device pnp 0.8 on end # hard_reset # end end # root_complex diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index 7147c69d76..58b052e33d 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,10 +89,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## @@ -134,7 +127,7 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000 #CK804 setting -default CK804_DEVN_BASE=0 +#default CK804_DEVN_BASE=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 diff --git a/src/mainboard/tyan/s2891/auto.c b/src/mainboard/tyan/s2891/auto.c index 4a8ef3f952..4637b4e9c6 100644 --- a/src/mainboard/tyan/s2891/auto.c +++ b/src/mainboard/tyan/s2891/auto.c @@ -87,7 +87,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 1 -#include "southbridge/nvidia/ck804/ck804_early_setup.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" @@ -136,6 +135,7 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); + #if CONFIG_LOGICAL_CPUS==1 id = get_node_core_id_x(); if(id.coreid == 0) { @@ -152,16 +152,19 @@ static void main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif + post_code(0x31); if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } + post_code(0x32); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -174,6 +177,7 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -190,5 +194,4 @@ static void main(unsigned long bist) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - } diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index ba2dfc1f8c..b78a899764 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -15,6 +15,7 @@ #include "northbridge/amd/amdk8/cpu_rev.c" //#define K8_HT_FREQ_1G_SUPPORT 1 +//#define K8_SCAN_PCI_BUS 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -84,6 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -259,6 +262,7 @@ void amd64_main(unsigned long bist) goto cpu_reset_x; } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else if (cpu_init_detected(nodeid)) { @@ -292,16 +296,14 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2891_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif + // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); @@ -312,20 +314,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -342,6 +334,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -386,7 +379,7 @@ cpu_reset_x: "movl %%ebx, %0\n\t" :"=a" (new_cpu_reset) ); - + /* We can not go back any more, we lost old stack data in cache as ram*/ if(new_cpu_reset==0) { print_debug("Use Ram as Stack now - done\r\n"); @@ -404,6 +397,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2891/irq_tables.c b/src/mainboard/tyan/s2891/irq_tables.c index d6f75a0950..0d880a23f6 100644 --- a/src/mainboard/tyan/s2891/irq_tables.c +++ b/src/mainboard/tyan/s2891/irq_tables.c @@ -18,7 +18,11 @@ const struct irq_routing_table intel_irq_routing_table = { 0x005c, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ +#if CK804_DEVN_BASE==0 0x5a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ +#else + 0x4a, +#endif { {1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, {0x5,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index e8d5f4ccc9..e62ec6eef1 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -52,22 +87,60 @@ void *smp_write_config_table(void *v) { device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_4 = 3; +#endif } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); if (dev) { bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -157,12 +230,9 @@ void *smp_write_config_table(void *v) pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; - - pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); } @@ -199,40 +269,51 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // #endif -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); // #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0); //24+4+0 = 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x0); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x0); // 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x2);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x2); // 26 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|2, apicid_8131_1, 0x0);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|3, apicid_8131_1, 0x1);// diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 20b58bce85..8a229a1269 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -92,10 +89,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c index d2512e9f61..25967056de 100644 --- a/src/mainboard/tyan/s2892/auto.c +++ b/src/mainboard/tyan/s2892/auto.c @@ -142,7 +142,6 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); - #if CONFIG_LOGICAL_CPUS==1 id = get_node_core_id_x(); if(id.coreid == 0) { @@ -150,6 +149,7 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else nodeid = lapicid(); @@ -164,7 +164,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -174,13 +174,14 @@ static void main(unsigned long bist) console_init(); /* Halt if there was a built in self test failure */ - report_bist_failure(bist); +// report_bist_failure(bist); setup_s2892_resource_map(); needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index 30a78f5a96..5158bccf55 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -86,6 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -295,15 +297,10 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2892_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); @@ -316,19 +313,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif #if 1 { @@ -346,6 +334,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -408,6 +397,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index b4f26aaeba..02754a1b34 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -7,6 +7,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -52,22 +87,60 @@ void *smp_write_config_table(void *v) { device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_4 = 3; +#endif } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); if (dev) { bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -152,6 +225,8 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); @@ -195,57 +270,77 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // #endif -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); // +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); // #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0);// +//Channel B of 8131 + + +//Onboard Broadcom NIC + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0);//24+4= 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|0, apicid_8131_2, 0x0);// +//SO DIMM PCI-X + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|0, apicid_8131_2, 0x0);//28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|1, apicid_8131_2, 0x1); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x2); // +//Slot 4 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x2); // 30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x0);// 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);// +//Channel A of 8131 + +//Slot 5 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); //28 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);//24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); // +//Slot 6 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); // 27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);// diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index e2d220201b..fc63823480 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -90,10 +87,6 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 -#default HARD_RESET_BUS=1 -#default HARD_RESET_DEVICE=4 -#default HARD_RESET_FUNCTION=0 - ## ## Build code to export a programmable irq routing table ## @@ -134,7 +127,7 @@ default CONFIG_LOGICAL_CPUS=1 default K8_E0_MEM_HOLE_SIZEK=0x100000 #CK804 setting -default CK804_DEVN_BASE=0 +#default CK804_DEVN_BASE=0 #VGA default CONFIG_CONSOLE_VGA=1 diff --git a/src/mainboard/tyan/s2895/auto.c b/src/mainboard/tyan/s2895/auto.c index b6f121e6e8..0a26f21735 100644 --- a/src/mainboard/tyan/s2895/auto.c +++ b/src/mainboard/tyan/s2895/auto.c @@ -14,7 +14,7 @@ #include "ram/ramtest.c" #include "northbridge/amd/amdk8/cpu_rev.c" -#define K8_HT_FREQ_1G_SUPPORT 1 +//#define K8_HT_FREQ_1G_SUPPORT 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -70,8 +70,9 @@ static void sio_gpio_setup(void){ unsigned value; +// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c + #if 1 - /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); @@ -117,10 +118,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 2 -#define CK804B_BUSN 0xc +#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 -#include "southbridge/nvidia/ck804/ck804_early_setup.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode @@ -192,11 +192,12 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); + post_code(0x30); #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 #if LIFT_BSP_APIC_ID == 0 - if( id.nodeid != 0 ) + if( id.nodeid != 0 ) //all except cores in node0 #endif lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); #endif @@ -213,7 +214,7 @@ static void main(unsigned long bist) #if LIFT_BSP_APIC_ID == 0 if(nodeid != 0) #endif - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 #endif @@ -223,16 +224,18 @@ static void main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif + post_code(0x31); if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } + post_code(0x32); lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -247,6 +250,7 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index fde94cc780..2cf73c333f 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -13,9 +13,10 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include "northbridge/amd/amdk8/cpu_rev.c" -#define K8_HT_FREQ_1G_SUPPORT 0 +#define K8_HT_FREQ_1G_SUPPORT 1 +#define K8_ALLOCATE_IO_RANGE 1 +//#define K8_SCAN_PCI_BUS 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -75,13 +76,11 @@ static void sio_gpio_setup(void){ unsigned value; +// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c -#if 1 - /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); -#endif } @@ -114,6 +113,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 @@ -121,8 +122,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 2 -//#define CK804B_BUSN 0x80 -#define CK804B_BUSN 0xc +#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -155,13 +155,18 @@ static void sio_setup(void) uint8_t byte; + /* LPC Variable Range Decode 1 0x400-0x47f */ + /* to make sure lpc47b397 gpio on device work */ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + /* subject decoding*/ byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + /* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + /*decode VAR1, serial 0 */ dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); @@ -311,7 +316,7 @@ void amd64_main(unsigned long bist) enable_lapic(); - init_timer(); +// init_timer(); #if CONFIG_LOGICAL_CPUS==1 @@ -323,10 +328,12 @@ void amd64_main(unsigned long bist) #endif if(id.coreid == 0) { if (cpu_init_detected(id.nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else #if ENABLE_APIC_EXT_ID == 1 @@ -337,6 +344,7 @@ void amd64_main(unsigned long bist) #endif if (cpu_init_detected(nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); cpu_reset = 1; goto cpu_reset_x; } @@ -355,6 +363,8 @@ void amd64_main(unsigned long bist) } } + init_timer(); // only do it it first CPU + lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -364,10 +374,6 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s2895_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif needs_reset = setup_coherent_ht_domain(); @@ -376,15 +382,7 @@ void amd64_main(unsigned long bist) start_other_cores(); #endif -#if CK804B_BUSN == 0x80 - // You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec - needs_reset |= ht_setup_chains(3); -#else - // automatically set that for you, but you might meet tight space - // Bcause it has two Ck804, we need to set CK804B_BUSN to 0xc (ht_setup_chains_x will let second CK804 use that bus num. - // otherwise ck804_eary_setup can not work rightly. needs_reset |= ht_setup_chains_x(); -#endif needs_reset |= ck804_early_setup_x(); @@ -394,20 +392,10 @@ void amd64_main(unsigned long bist) } enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); -#if 0 - dump_pci_devices(); -#endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -424,6 +412,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -486,6 +475,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_err("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c index cf1a438dc1..aa16866763 100644 --- a/src/mainboard/tyan/s2895/irq_tables.c +++ b/src/mainboard/tyan/s2895/irq_tables.c @@ -403,6 +403,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } + printk_info("done.\n"); + return (unsigned long) pirq_info; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index f6b534d866..810e234af6 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -8,6 +8,41 @@ #include <cpu/amd/dualcore.h> #endif + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -62,21 +97,71 @@ void *smp_write_config_table(void *v) device_t dev; + bus_ck804_0 = node_link_to_bus(0, 0); + if (bus_ck804_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_ck804_0 = 1; + } /* CK804 */ - bus_ck804_0 = 1; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); if (dev) { bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if 0 + bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_2++; +#else bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_5++; +#endif } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09); bus_ck804_1 = 2; +#if 0 + bus_ck804_2 = 3; +#else bus_ck804_5 = 3; +#endif + + } +#if 0 + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_3++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b); + + bus_ck804_3 = bus_ck804_2+1; + } + + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_4++; + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c); + + bus_ck804_4 = bus_ck804_3+1; + } + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); + if (dev) { + bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804_5++; } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d); + + bus_ck804_5 = bus_ck804_4+1; + } +#endif dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0)); if (dev) { @@ -119,6 +204,59 @@ void *smp_write_config_table(void *v) /* CK804b */ +#if 0 + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0)); + if (dev) { + bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_2++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09); + + bus_ck804b_1 = bus_ck804b_0+1; + bus_ck804b_2 = bus_ck804b_0+2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0)); + if (dev) { + bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_3++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b); + + bus_ck804b_2 = bus_ck804b_0+1; + bus_ck804b_3 = bus_ck804b_0+2; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0)); + if (dev) { + bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_4++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c); + + bus_ck804b_4 = bus_ck804b_3+1; + } + + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0)); + if (dev) { + bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804b_5++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d); + + bus_ck804b_5 = bus_ck804b_4+1; + } + +#endif + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0)); if (dev) { bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -168,7 +306,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } - dword = 0x0120d218; + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; @@ -229,58 +367,77 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); +// 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // 17 +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // 16 #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 -#if 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // +#if CK804_DEVN_BASE == 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);//18+24+4+4=50 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // 16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // 17 +#else + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x10); #endif - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); // +//Channel B of 8131 + +//Slot 4 PCI-X 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); //24+4 = 28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x2); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x3); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); // +//Slot 5 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); //24+4+1 = 29 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|2, apicid_8131_2, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|3, apicid_8131_2, 0x0);// +//OnBoard LSI SCSI + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // 24+4+2 = 30 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); // 31 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); +//Channel A of 8131 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // +//Slot 6 PCIX 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // 24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|2, apicid_8131_1, 0x2);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|3, apicid_8131_1, 0x3);// diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index 3b3806f6ac..e3c5b03b40 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -##object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index f3d73515ee..fc98b83255 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -87,14 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 diff --git a/src/mainboard/tyan/s4880/auto.c b/src/mainboard/tyan/s4880/auto.c index fc1bf58e91..3e0d4825df 100644 --- a/src/mainboard/tyan/s4880/auto.c +++ b/src/mainboard/tyan/s4880/auto.c @@ -95,65 +95,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } -#if 0 -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - uint32_t ret=0x00010101; /* default row entry */ - -/* - (L1) (L2) - CPU3-------------CPU1 - (L0)| |(L0) - | | - | | - | | - | | - (L0)| |(L0) - CPU2-------------CPU0---------8131----------8111 - (L2) (L1) (L2) -*/ - - /* Link0 of CPU0 to Link0 of CPU1 */ - /* Link1 of CPU0 to Link2 of CPU2 */ - /* Link2 of CPU1 to Link1 of CPU3 */ - /* Link0 of CPU2 to Link0 of CPU3 */ - - static const unsigned int rows_4p[4][4] = { - { 0x00070101, 0x00010202, 0x00030404, 0x00010204 }, - { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 }, - { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 }, - { 0x00010204, 0x00030404, 0x00010202, 0x00070101 } - }; - - if (!(node>=maxnodes || row>=maxnodes)) { - ret=rows_4p[node][row]; - } - - return ret; -} -#endif - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -161,6 +102,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB , 0x01, device); smbus_write_byte(SMBUS_HUB , 0x03, 0); } +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + smbus_write_byte(SMBUS_HUB , 0x01, device); + smbus_write_byte(SMBUS_HUB , 0x03, 0); +} +#endif static inline int spd_read_byte(unsigned device, unsigned address) { @@ -308,22 +257,19 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched start_other_cores(); #endif -#if 0 - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); -#else - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); -#endif if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); } +#if 0 + dump_pci_devices(); +#endif enable_smbus(); memreset_setup(); diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index f39ff15b4d..bddcd08820 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -325,6 +325,7 @@ void amd64_main(unsigned long bist) enable_lapic(); init_timer(); +// post_code(0x30); #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 @@ -355,7 +356,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -380,9 +380,9 @@ void amd64_main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); if (needs_reset) { diff --git a/src/mainboard/tyan/s4880/reset.c b/src/mainboard/tyan/s4880/reset.c new file mode 100644 index 0000000000..63958185f6 --- /dev/null +++ b/src/mainboard/tyan/s4880/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 2); +} diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 95ef0464fe..18fec090cf 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -43,7 +43,7 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o +object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 56a2548228..0c5571aa07 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS @@ -31,9 +28,9 @@ uses USE_OPTION_TABLE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR -uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses LINUXBIOS_EXTRA_VERSION @@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_HARD_RESET=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=3 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 - -## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -153,8 +143,8 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s4882" default MAINBOARD_VENDOR="Tyan" +default MAINBOARD_PART_NUMBER="s4882" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 diff --git a/src/mainboard/tyan/s4882/auto.c b/src/mainboard/tyan/s4882/auto.c index 21d459b6e4..e8d46e7961 100644 --- a/src/mainboard/tyan/s4882/auto.c +++ b/src/mainboard/tyan/s4882/auto.c @@ -26,26 +26,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); -} + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); -static void soft2_reset(void) -{ set_bios_reset(); - pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -73,6 +99,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -194,7 +221,7 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 set_apicid_cpuid_lo(); - id = get_node_core_id_x(); + id = get_node_core_id_x(); // that is initid #if ENABLE_APIC_EXT_ID == 1 if(id.coreid == 0) { enable_apic_ext_id(id.nodeid); @@ -213,7 +240,7 @@ static void main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 #if LIFT_BSP_APIC_ID == 0 - if( id.nodeid != 0 ) + if( id.nodeid != 0 ) //all except cores in node0 #endif lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); #endif @@ -241,7 +268,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -257,10 +284,10 @@ static void main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\r\n"); diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index bbcc49a9cf..234e3a0a58 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -37,20 +37,52 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + static void hard_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); + set_bios_reset(); /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + pci_write_config8(dev, 0x41, 0xf1); /* reset */ outb(0x0e, 0x0cf9); } static void soft_reset(void) { + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); + set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + pci_write_config8(dev, 0x47, 1); } static void memreset_setup(void) @@ -77,6 +109,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -109,6 +142,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" #endif #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -325,7 +360,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -337,22 +371,15 @@ void amd64_main(unsigned long bist) } } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s4882_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif - + needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 @@ -387,6 +414,7 @@ void amd64_main(unsigned long bist) } #endif +#if 1 cpu_reset_x: @@ -450,6 +478,7 @@ cpu_reset_x: copy_and_run(new_cpu_reset); /* We will not return */ } +#endif print_debug("should not be here -\r\n"); diff --git a/src/mainboard/tyan/s4882/reset.c b/src/mainboard/tyan/s4882/reset.c new file mode 100644 index 0000000000..7f58d01410 --- /dev/null +++ b/src/mainboard/tyan/s4882/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 1); +} |