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-rw-r--r--src/mainboard/amd/persimmon/romstage.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index e3ed847fdb..da2db64071 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu())
+ {
+ __outdword (0xcf8, 0x8000a3b8);
+ __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+ }
+
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{