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-rw-r--r--src/mainboard/siemens/mc_apl1/brd_gpio.h5
-rw-r--r--src/mainboard/siemens/mc_apl1/gpio.c13
2 files changed, 6 insertions, 12 deletions
diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h
index 0858a1add2..5cf07a66c1 100644
--- a/src/mainboard/siemens/mc_apl1/brd_gpio.h
+++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h
@@ -14,6 +14,9 @@
* GNU General Public License for more details.
*/
+#ifndef _BRD_GPIO_H_
+#define _BRD_GPIO_H_
+
#include <soc/gpio.h>
/*
@@ -22,3 +25,5 @@
*/
const struct pad_config *brd_gpio_table(size_t *num);
const struct pad_config *brd_early_gpio_table(size_t *num);
+
+#endif /* _BRD_GPIO_H_ */
diff --git a/src/mainboard/siemens/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/gpio.c
index bdeff73798..b872b8d832 100644
--- a/src/mainboard/siemens/mc_apl1/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/gpio.c
@@ -69,7 +69,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
- PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */
+ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */
/* SMBus */
PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */
@@ -350,17 +350,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */
PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */
- /* JTAG interface. */
- PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* TCK */
- PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* TRST_B */
- PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), /* TMS */
- PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), /* TDI */
- PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), /* CX_PMODE */
- PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), /* CX_PREQ_B */
- PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), /* JTAGX */
- PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), /* CX_PRDY_B */
- PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), /* TDO */
-
/* CNV bridge described into IAFW Vol2. */
/* GPIO_[216:219] described into EDS Vol1. */
PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */