diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 15 | ||||
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 15 |
2 files changed, 18 insertions, 12 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index bb925cebe1..428779a470 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 89fcff8ccd..c4b89af4aa 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end |