diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/nyan/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_big/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_blaze/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_blaze/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 21 |
5 files changed, 17 insertions, 13 deletions
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 0baf2b74f8..fffe0de282 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -46,8 +46,6 @@ static void __attribute__((noinline)) romstage(void) timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2_cache(); - console_init(); exception_init(); @@ -58,6 +56,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ u32 dram_size = dram_end - dram_start; + configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0baf2b74f8..fffe0de282 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -46,8 +46,6 @@ static void __attribute__((noinline)) romstage(void) timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2_cache(); - console_init(); exception_init(); @@ -58,6 +56,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ u32 dram_size = dram_end - dram_start; + configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 789937ff2f..9557ec4806 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -93,6 +93,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config VBOOT_RAMSTAGE_INDEX hex + default 0x3 if VBOOT2_VERIFY_FIRMWARE default 0x2 config FLASHMAP_OFFSET diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index daf9039a32..8cfa2985cc 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -30,9 +30,9 @@ subdirs-y += bct bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c -bootblock-y += early_configs.c verstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += early_configs.c verstage-y += reset.c romstage-y += early_configs.c diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index cfeb77a523..65596a28d3 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -46,8 +46,6 @@ static void __attribute__((noinline)) romstage(void) timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2_cache(); - console_init(); exception_init(); @@ -58,21 +56,25 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ u32 dram_size = dram_end - dram_start; +#if !CONFIG_VBOOT2_VERIFY_FIRMWARE + configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); - /* DRAM is cached. */ - mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); - /* A window for DMA is uncached. */ - mmu_config_range(CONFIG_DRAM_DMA_START >> 20, - CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end < 4096) mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); +#endif + + /* DRAM is cached. */ + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); /* * A watchdog reset only resets part of the system so it ends up in @@ -91,8 +93,9 @@ static void __attribute__((noinline)) romstage(void) early_mainboard_init(); #if CONFIG_VBOOT2_VERIFY_FIRMWARE - vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); + entry = vboot_load_ramstage(); #else + early_mainboard_init(); vboot_verify_firmware(romstage_handoff_find_or_add()); #endif @@ -102,7 +105,9 @@ static void __attribute__((noinline)) romstage(void) /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ void main(void) { +#if !CONFIG_VBOOT2_VERIFY_FIRMWARE asm volatile ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); +#endif romstage(); } |