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-rw-r--r--src/mainboard/amd/gardenia/Makefile.inc5
-rw-r--r--src/mainboard/amd/gardenia/bootblock/bootblock.c27
-rw-r--r--src/mainboard/amd/gardenia/gpio.c (renamed from src/mainboard/amd/gardenia/bootblock/gpio.c)14
-rw-r--r--src/mainboard/amd/gardenia/gpio.h22
-rw-r--r--src/mainboard/amd/gardenia/mainboard.c12
-rw-r--r--src/mainboard/google/kahlee/bootblock/bootblock.c6
-rw-r--r--src/mainboard/google/kahlee/mainboard.c5
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c15
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h3
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/gpio.c12
10 files changed, 102 insertions, 19 deletions
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index cceb84c48e..fe3a8c8a46 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -13,13 +13,14 @@
# GNU General Public License for more details.
#
-bootblock-y += bootblock/gpio.c
+bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/OemCustomize.c
+bootblock-y += gpio.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
-ramstage-y += bootblock/gpio.c
ramstage-y += BiosCallOuts.c
+ramstage-y += gpio.c
ramstage-y += OemCustomize.c
ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c
diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c
new file mode 100644
index 0000000000..dae59b78d8
--- /dev/null
+++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/southbridge.h>
+
+#include "../gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+ size_t num_gpios;
+ const struct soc_amd_stoneyridge_gpio *gpios;
+ gpios = early_gpio_table(&num_gpios);
+ sb_program_gpios(gpios, num_gpios);
+}
diff --git a/src/mainboard/amd/gardenia/bootblock/gpio.c b/src/mainboard/amd/gardenia/gpio.c
index 54d966e251..2d73ee08d2 100644
--- a/src/mainboard/amd/gardenia/bootblock/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -19,6 +19,8 @@
#include <stdlib.h>
#include <soc/gpio.h>
+#include "gpio.h"
+
/*
* As a rule of thumb, GPIO pins used by coreboot should be initialized at
* bootblock while GPIO pins used only by the OS should be initialized at
@@ -46,12 +48,14 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
{GPIO_70, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
};
-const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)
+const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
+}
+
+const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size)
{
- if (GPIO_TABLE_BOOTBLOCK) {
- *size = ARRAY_SIZE(gpio_set_stage_reset);
- return gpio_set_stage_reset;
- }
*size = ARRAY_SIZE(gpio_set_stage_ram);
return gpio_set_stage_ram;
}
diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h
new file mode 100644
index 0000000000..f3869448f5
--- /dev/null
+++ b/src/mainboard/amd/gardenia/gpio.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size);
+const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size);
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 824fd9d979..71fa257318 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -18,6 +18,9 @@
#include <arch/acpi.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
+#include <soc/southbridge.h>
+
+#include "gpio.h"
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -75,7 +78,13 @@ static void pirq_setup(void)
picr_data_ptr = mainboard_picr_data;
}
-
+static void mainboard_init(void *chip_info)
+{
+ size_t num_gpios;
+ const struct soc_amd_stoneyridge_gpio *gpios;
+ gpios = gpio_table(&num_gpios);
+ sb_program_gpios(gpios, num_gpios);
+}
/*************************************************
* enable the dedicated function in gardenia board.
@@ -90,5 +99,6 @@ static void gardenia_enable(device_t dev)
}
struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
.enable_dev = gardenia_enable,
};
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 90c8acbabf..244abe051f 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -13,12 +13,18 @@
* GNU General Public License for more details.
*/
+#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <soc/southbridge.h>
#include <variant/ec.h>
void bootblock_mainboard_init(void)
{
+ size_t num_gpios;
+ const struct soc_amd_stoneyridge_gpio *gpios;
+ gpios = variant_early_gpio_table(&num_gpios);
+ sb_program_gpios(gpios, num_gpios);
+
/* Enable the EC as soon as we have visibility */
mainboard_ec_init();
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index b7adfc026a..aa8d080b6a 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -156,11 +156,16 @@ static void mainboard_init(void *chip_info)
const struct sci_source *gpes;
size_t num;
int boardid = board_id();
+ size_t num_gpios;
+ const struct soc_amd_stoneyridge_gpio *gpios;
printk(BIOS_INFO, "Board ID: %d\n", boardid);
mainboard_ec_init();
+ gpios = variant_gpio_table(&num_gpios);
+ sb_program_gpios(gpios, num_gpios);
+
gpes = get_gpe_table(&num);
gpe_configure_sci(gpes, num);
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index a6bcea5c86..1e1f34b005 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -258,13 +258,16 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
{ GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT },
};
-const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio
- *board_get_gpio(size_t *size)
+const __attribute__((weak))
+struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
+}
+
+const __attribute__((weak))
+struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)
{
- if (GPIO_TABLE_BOOTBLOCK) {
- *size = ARRAY_SIZE(gpio_set_stage_reset);
- return gpio_set_stage_reset;
- }
*size = ARRAY_SIZE(gpio_set_stage_ram);
return gpio_set_stage_ram;
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
index bf14ef4d7c..83ee1190e3 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
@@ -19,6 +19,7 @@
#include <stddef.h>
#include <soc/smi.h>
+#include <soc/southbridge.h>
#include <amdblocks/agesawrapper.h>
const struct sci_source *get_gpe_table(size_t *num);
@@ -26,5 +27,7 @@ uint8_t variant_memory_sku(void);
int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
int variant_get_xhci_oc_map(uint16_t *usb_oc_map);
int variant_get_ehci_oc_map(uint16_t *usb_oc_map);
+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size);
+const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);
#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index e357c7e2c3..d1cc017c93 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -96,12 +96,14 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
{GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
};
-const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)
+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
+}
+
+const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)
{
- if (GPIO_TABLE_BOOTBLOCK) {
- *size = ARRAY_SIZE(gpio_set_stage_reset);
- return gpio_set_stage_reset;
- }
*size = ARRAY_SIZE(gpio_set_stage_ram);
return gpio_set_stage_ram;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 04:41:35 +0000