summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/hp/Kconfig3
-rw-r--r--src/mainboard/hp/abm/BiosCallOuts.c256
-rw-r--r--src/mainboard/hp/abm/Kconfig31
-rw-r--r--src/mainboard/hp/abm/OptionsIds.h5
-rw-r--r--src/mainboard/hp/abm/PlatformGnbPcie.c9
-rw-r--r--src/mainboard/hp/abm/acpi/mainboard.asl7
-rw-r--r--src/mainboard/hp/abm/acpi/usb_oc.asl2
-rw-r--r--src/mainboard/hp/abm/board_info.txt5
-rw-r--r--src/mainboard/hp/abm/buildOpts.c28
-rw-r--r--src/mainboard/hp/abm/cmos.layout2
-rw-r--r--src/mainboard/hp/abm/devicetree.cb82
-rw-r--r--src/mainboard/hp/abm/dsdt.asl2
-rw-r--r--src/mainboard/hp/abm/irq_tables.c2
-rw-r--r--src/mainboard/hp/abm/mainboard.c93
-rw-r--r--src/mainboard/hp/abm/mptable.c2
-rw-r--r--src/mainboard/hp/abm/romstage.c49
16 files changed, 187 insertions, 391 deletions
diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig
index 4b391ad4d0..3efd1dd29d 100644
--- a/src/mainboard/hp/Kconfig
+++ b/src/mainboard/hp/Kconfig
@@ -3,6 +3,8 @@ if VENDOR_HP
choice
prompt "Mainboard model"
+config BOARD_HP_ABM
+ bool "ABM"
config BOARD_HP_DL145_G1
bool "ProLiant DL145 G1"
config BOARD_HP_DL145_G3
@@ -17,6 +19,7 @@ config BOARD_HP_PAVILION_M6_1035DX
endchoice
+source "src/mainboard/hp/abm/Kconfig"
source "src/mainboard/hp/dl145_g1/Kconfig"
source "src/mainboard/hp/dl145_g3/Kconfig"
source "src/mainboard/hp/dl165_g6_fam10/Kconfig"
diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c
index 53b687159b..d55bc06f99 100644
--- a/src/mainboard/hp/abm/BiosCallOuts.c
+++ b/src/mainboard/hp/abm/BiosCallOuts.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <device/azalia.h>
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
@@ -48,257 +48,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/**
- * CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip
- */
-static const CODEC_ENTRY Alc662_VerbTbl[] =
-{
- { 0x14, /*01014010*/ /* Port D - green headphone jack */
- (AZALIA_PINCFG_PORT_JACK << 30)
- | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
- | (AZALIA_PINCFG_DEVICE_LINEOUT << 20)
- | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
- | (AZALIA_PINCFG_COLOR_GREEN << 12)
- | (1 << 4)
- | (0 << 0)
- },
- { 0x15, /*0x90170120*/ /* Port A - white speaker header */
- (AZALIA_PINCFG_PORT_FIXED << 30)
- | (AZALIA_PINCFG_LOCATION_INTERNAL << 24)
- | (AZALIA_PINCFG_DEVICE_SPEAKER << 20)
- | (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16)
- | (AZALIA_PINCFG_COLOR_WHITE << 12)
- | (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8)
- | (2 << 4)
- | (0 << 0)
- },
- { 0x16, 0x411111F0 }, /* Port G - not connected */
- { 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */
- (AZALIA_PINCFG_PORT_JACK << 30)
- | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
- | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
- | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
- | (AZALIA_PINCFG_COLOR_PINK << 12)
- | (4 << 4)
- | (0 << 0)
- },
- { 0x19, /*0x02A19050*/ /* Port F - front panel header mic */
- (AZALIA_PINCFG_PORT_NC << 30)
- | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
- | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
- | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
- | (AZALIA_PINCFG_COLOR_PINK << 12)
- | (5 << 4)
- | (0 << 0)
- },
- { 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */
- (AZALIA_PINCFG_PORT_NC << 30)
- | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
- | (AZALIA_PINCFG_DEVICE_LINEIN << 20)
- | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
- | (AZALIA_PINCFG_COLOR_BLUE << 12)
- | (4 << 4)
- | (0xF << 0)
- },
- { 0x1B, /*0x02214030*/ /* Port E - front panel line-out */
- (AZALIA_PINCFG_PORT_NC << 30)
- | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
- | (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
- | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
- | (AZALIA_PINCFG_COLOR_GREEN << 12)
- | (3 << 4)
- | (0 << 0)
- },
- { 0x1C, 0x411111F0 }, /* CD-in - Not Connected */
- { 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */
- { 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */
- { 0xFF, 0xFFFFFFFF },
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
- {0x10ec0662, (CODEC_ENTRY*)Alc662_VerbTbl},
- {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE 0
-#define FAN_INPUT_TEMP0 1
-#define FAN_INPUT_TEMP1 2
-#define FAN_INPUT_TEMP2 3
-#define FAN_INPUT_TEMP3 4
-#define FAN_INPUT_TEMP0_FILTER 5
-#define FAN_INPUT_ZERO 6
-#define FAN_INPUT_DISABLED 7
-
-#define FAN_AUTOMODE (1 << 0)
-#define FAN_LINEARMODE (1 << 1)
-#define FAN_STEPMODE ~(1 << 1)
-#define FAN_POLARITY_HIGH (1 << 2)
-#define FAN_POLARITY_LOW ~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ 0x0
-#define FREQ_25KHZ 0x1
-#define FREQ_23KHZ 0x2
-#define FREQ_21KHZ 0x3
-#define FREQ_29KHZ 0x4
-#define FREQ_18KHZ 0x5
-#define FREQ_100HZ 0xF7
-#define FREQ_87HZ 0xF8
-#define FREQ_58HZ 0xF9
-#define FREQ_44HZ 0xFA
-#define FREQ_35HZ 0xFB
-#define FREQ_29HZ 0xFC
-#define FREQ_22HZ 0xFD
-#define FREQ_14HZ 0xFE
-#define FREQ_11HZ 0xFF
-
-/* imb_a180 Hardware Monitor Fan Control
- * Hardware limitation:
- * HWM failed to read the input temperture vi I2C,
- * if other software switch the I2C switch by mistake or intention.
- * We recommend to using IMC to control Fans, instead of HWM.
- */
-#if 0
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
- FCH_HWM_FAN_CTR oem_factl[5] = {
- /* temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
- /* imb_a180 FanOUT0 Fan header J32 */
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- /* imb_a180 FanOUT1 Fan header J31*/
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- };
- LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
-
- /* Enable IMC fan control. the recommand way */
-#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1)
- /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
- FchParams->Hwm.HwMonitorEnable = TRUE;
- FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
-
- FchParams->Imc.ImcEnable = TRUE;
- FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
-
- LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
- /* Thermal Zone Parameter */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
-
- /* IMC Fan Policy temperature thresholds */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
- /* IMC Fan Policy PWM Settings */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */
-
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
-
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
-
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
-
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
-
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
-
- /* IMC Function */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8;
-
- /* NOTE:
- * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
- * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
- * so we remove it from AGESA code. Please Seee FchInitLateHwm.
- */
-
-#else /* HWM fan control, the way not recommand */
- FchParams->Imc.ImcEnable = FALSE;
- FchParams->Hwm.HwMonitorEnable = TRUE;
- FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
-
-#endif /* CONFIG_HUDSON_IMC_FWM */
-}
-#endif
-
-/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
@@ -318,12 +67,9 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
- /* Azalia Controller OEM Codec Table Pointer */
- FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList;
/* Azalia Controller Front Panel OEM Table Pointer */
/* Fan Control */
- //oem_fan_control(FchParams_env);
/* XHCI configuration */
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index f88ce040f0..83ce7a8a16 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -1,7 +1,8 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012-2014 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Sage Electronic Engineering, LLC
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -17,29 +18,27 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-if BOARD_ASROCK_IMB_A180
+if BOARD_HP_ABM
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
- select SUPERIO_WINBOND_W83627UHG
+ select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_4096
- select GFXUMA
+ select BOARD_ROMSIZE_KB_8192
config MAINBOARD_DIR
string
- default asrock/imb-a180
+ default hp/abm
config MAINBOARD_PART_NUMBER
string
- default "IMB-A180"
+ default "ABM"
config HW_MEM_HOLE_SIZEK
hex
@@ -57,20 +56,8 @@ config IRQ_SLOT_COUNT
int
default 11
-config ONBOARD_VGA_IS_PRIMARY
- bool
- default y
-
config HUDSON_LEGACY_FREE
bool
- default y
-
-# bit 1,0 - pin 0
-# bit 3,2 - pin 1
-# bit 5,4 - pin 2
-# bit 7,6 - pin 3
-config AZ_PIN
- hex
- default 0x2
+ default n
-endif # BOARD_ASROCK_IMB_A180
+endif # BOARD_HP_ABM
diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h
index 0a1d32850a..58800307d3 100644
--- a/src/mainboard/hp/abm/OptionsIds.h
+++ b/src/mainboard/hp/abm/OptionsIds.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
@@ -64,4 +65,4 @@
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80
-#endif
+#endif /* _OPTION_IDS_H_ */
diff --git a/src/mainboard/hp/abm/PlatformGnbPcie.c b/src/mainboard/hp/abm/PlatformGnbPcie.c
index da1910e96c..36dfb13bb9 100644
--- a/src/mainboard/hp/abm/PlatformGnbPcie.c
+++ b/src/mainboard/hp/abm/PlatformGnbPcie.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -88,16 +89,10 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
},
/* DP1 to FCH */
{
- 0,
+ DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
},
- /* DP2 to HDMI1/DP */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
- },
};
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl
index 05523fb19a..ca3fd6ebb6 100644
--- a/src/mainboard/hp/abm/acpi/mainboard.asl
+++ b/src/mainboard/hp/abm/acpi/mainboard.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -35,7 +35,4 @@ Name(PMOD, One) /* Assume APIC */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
- Field(GP0B, ByteAcc, NoLock, Preserve) {
- , 11,
- USBS, 1,
-}
+ Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, }
diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl
index 7b5b1c67d0..4d9af01e38 100644
--- a/src/mainboard/hp/abm/acpi/usb_oc.asl
+++ b/src/mainboard/hp/abm/acpi/usb_oc.asl
@@ -41,7 +41,7 @@ Name(UOM9, 6)
/* USB Overcurrent GPEs */
-#if 0 /* TODO: Update for imba180 */
+#if 0 /* TODO: Update */
Method(UCOC, 0) {
Sleep(20)
Store(0x13,CMTI)
diff --git a/src/mainboard/hp/abm/board_info.txt b/src/mainboard/hp/abm/board_info.txt
new file mode 100644
index 0000000000..38fedd5e66
--- /dev/null
+++ b/src/mainboard/hp/abm/board_info.txt
@@ -0,0 +1,5 @@
+Category: mini
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index 06199e0bfa..8ceb3e6046 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -76,7 +77,7 @@
#define BLDOPT_REMOVE_SRAT FALSE //TRUE
#define BLDOPT_REMOVE_SLIT FALSE //TRUE
#define BLDOPT_REMOVE_WHEA FALSE //TRUE
-#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_CDIT TRUE
#define BLDOPT_REMOVE_DMI TRUE
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
@@ -153,7 +154,7 @@
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
#define BLDCFG_IOMMU_SUPPORT FALSE
#define OPTION_GFX_INIT_SVIEW FALSE
@@ -344,11 +345,20 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
-GPIO_CONTROL imba180_gpio[] = {
- {183, Function1, GpioIn | GpioOutEnB | PullUpB},
+GPIO_CONTROL hp_abm_gpio[] = {
+ { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED
+ { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID
+ { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH
+ { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT
+ { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L
+ { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC
+ { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L
+ { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT
+ { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT
+ { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
{-1}
};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0])
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
@@ -441,11 +451,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_4),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout
index f6b5806d97..5520564051 100644
--- a/src/mainboard/hp/abm/cmos.layout
+++ b/src/mainboard/hp/abm/cmos.layout
@@ -15,7 +15,7 @@
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#*****************************************************************************
entries
diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb
index 6d6875d425..eb18a05c72 100644
--- a/src/mainboard/hp/abm/devicetree.cb
+++ b/src/mainboard/hp/abm/devicetree.cb
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2013 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Sage Electronic Engineering, LLC
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -28,76 +29,55 @@ chip northbridge/amd/agesa/family16kb/root_complex
chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
- device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIe Host Bridge
- device pci 2.1 on end # x4 PCIe slot
- device pci 2.2 on end # mPCIe slot
- device pci 2.3 on end # Realtek NIC
- device pci 2.4 on end # Edge Connector
- device pci 2.5 on end # Edge Connector
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 off end # unused
+ device pci 2.2 on end # GPP0: NIC
+ device pci 2.3 on end # GPP1: NIC
+ device pci 2.4 off end # GPP2: unused
+ device pci 2.5 off end # GPP3: unused
end #chip northbridge/amd/agesa/family16kb
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
- device pci 10.0 on end # XHCI HC0
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
+ chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
end # SM
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on
- chip superio/winbond/w83627uhg
- device pnp 2e.0 off end # FDC
- device pnp 2e.1 off end # LPT1
- device pnp 2e.2 on # COM1
+ device pci 14.2 off end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d
+ device pnp 4e.0 off end # FDC
+ device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 on # COM2
+ device pnp 4e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 2e.5 on # KEYBRD
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 on # COM3
- io 0x60 = 0x3e8
- irq 0x70 = 4
- end
- device pnp 2e.7 off end # GPIO
- device pnp 2e.8 off end # WDT
- device pnp 2e.9 off end # GPIO
- device pnp 2e.a off end # ACPI
- device pnp 2e.b off end # HWMON
- device pnp 2e.c off end # PECI
- device pnp 2e.d on # COM4
+ device pnp 4e.7 off end # GPIO
+ device pnp 4e.8 off end # GPIO/WDT
+ device pnp 4e.f off end # GPIO
+ device pnp 4e.10 off end # COM3 used by port 80
+ device pnp 4e.11 on # COM4
io 0x60 = 0x2e8
irq 0x70 = 3
end
- device pnp 2e.e on # COM5
- io 0x60 = 0x3e0
- irq 0x70 = 4
- end
- device pnp 2e.f on # COM6
- io 0x60 = 0x2e0
- irq 0x70 = 3
- end
- end # w83627uhg
- end # LPC 0x439d
- device pci 14.7 on end # SD
+ device pnp 4e.14 off end # PORT80
+ register "irq_trigger_type" = "0" # 0 edge, 1 level
+ end # nct5104d
+ end #LPC
+ device pci 14.7 off end # SD
+ device pci 16.0 on end # USB
+ device pci 16.2 on end # USB
end #chip southbridge/amd/hudson
device pci 18.0 on end
@@ -108,10 +88,8 @@ chip northbridge/amd/agesa/family16kb/root_complex
device pci 18.5 on end
register "spdAddrLookup" = "
{
- { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
- { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses
}"
-
end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
end #domain
end #northbridge/amd/agesa/family16kb/root_complex
diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl
index cecaa59631..d2d8122631 100644
--- a/src/mainboard/hp/abm/dsdt.asl
+++ b/src/mainboard/hp/abm/dsdt.asl
@@ -15,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* DefinitionBlock Statement */
diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c
index c1c25baf02..22ed1ab0a8 100644
--- a/src/mainboard/hp/abm/irq_tables.c
+++ b/src/mainboard/hp/abm/irq_tables.c
@@ -14,7 +14,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c
index cf02528916..adb70930c8 100644
--- a/src/mainboard/hp/abm/mainboard.c
+++ b/src/mainboard/hp/abm/mainboard.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,16 +22,97 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/agesawrapper.h>
+#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/agesa/hudson/pci_devs.h>
+#include <northbridge/amd/agesa/family16kb/pci_devs.h>
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */
+ [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
+ [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */
+ [0x40] = 0x0B,0x0B, /* IDE, SATA */
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
+ [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */
+ [0x40] = 0x11,0x13, /* IDE, SATA */
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device. Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01. This index will define
+ * the interrupt that it should use. Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.2 */
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.3 */
+ {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.4 */
+ {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.5 */
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
+ {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCIB: 14.4 */
+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
+ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+/* TODO: mainboard specific SB AGESA callback */
+void set_pcie_reset(void)
+{
+}
+
+/* TODO: mainboard specific SB AGESA callback */
+void set_pcie_dereset(void)
+{
+}
/**********************************************
- * enable the dedicated function in mainboard.
+ * Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(device_t dev)
{
@@ -38,6 +120,9 @@ static void mainboard_enable(device_t dev)
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index d9ca7b74a2..629888ae08 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -14,7 +14,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 1ba1104eb0..5e3044a0e5 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
@@ -31,29 +32,21 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/lapic.h"
-#include "southbridge/amd/agesa/hudson/hudson.h"
-#include "cpu/amd/agesa/s3_resume.h"
-#include "cbmem.h"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627uhg/w83627uhg.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cbmem.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val, t32;
u32 *addr32;
- /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
- * even though the register is not documented in the Kabini BKDG.
- * Otherwise the serial output is bad code.
- */
- //outb(0xD2, 0xcd6);
- //outb(0x00, 0xcd7);
amd_initmmio();
@@ -65,27 +58,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ outb(0x01, 0xcd7);
- /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
+ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
+ /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
- t32 &= 0xfff8ffff;
+ t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
+ t32 |= 0x00010000; // Set bit 16 for 25MHz
*addr32 = t32;
- /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
+ /* Enable Auxiliary OSCOUT1/OSCOUT2 */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
- t32 &= 0xffffbffb;
+ t32 &= 0xffffff7b; // clear 2, 7
*addr32 = t32;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
post_code(0x31);
- /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
+ nct5104d_enable_uartd(SERIAL_DEV);
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
@@ -98,11 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
- int i;
- for(i = 0; i < 200000; i++)
- val = inb(0xcd6);
-
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x38);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 08:21:53 +0000