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-rw-r--r--src/mainboard/ocp/tiogapass/bootblock.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c
index d507422d30..67808ef72a 100644
--- a/src/mainboard/ocp/tiogapass/bootblock.c
+++ b/src/mainboard/ocp/tiogapass/bootblock.c
@@ -4,6 +4,7 @@
#include <bootblock_common.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
#include <intelblocks/pcr.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -13,6 +14,8 @@
/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
+#define ASPEED_CONFIG_INDEX 0x2E
+#define ASPEED_CONFIG_DATA 0x2F
static void enable_espi_lpc_io_windows(void)
{
@@ -54,6 +57,14 @@ void bootblock_mainboard_early_init(void)
enable_espi_lpc_io_windows();
/* Configure appropriate physical port of SuperIO chip off BMC */
- const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
+ const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX,
+ com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+ /* Port 80h direct to GPIO for LED display */
+ const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO);
+ aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH);
+
+ /* Enable UART function pin */
+ aspeed_enable_uart_pin(serial_dev);
}