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-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c2
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c2
-rw-r--r--src/mainboard/google/beltino/devicetree.cb4
-rw-r--r--src/mainboard/google/beltino/romstage.c4
-rw-r--r--src/mainboard/google/slippy/devicetree.cb4
-rw-r--r--src/mainboard/google/slippy/romstage.c3
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c2
-rw-r--r--src/mainboard/lenovo/t440p/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t440p/romstage.c2
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c2
10 files changed, 9 insertions, 17 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 9bdb8dd4bd..119d007cf1 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -27,8 +27,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 0573b6b171..deb6ec941b 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -25,8 +25,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index f4c9e850ab..304f3cf38f 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -9,6 +9,10 @@ chip northbridge/intel/haswell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ register "dq_pins_interleaved" = "true"
+
+ register "usb_xhci_on_resume" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 8410d04923..ee146301ec 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -48,10 +48,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
- pei_data->dq_pins_interleaved = 1;
- pei_data->usb_xhci_on_resume = 1;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 3d98d745a3..e22a41ebc2 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -14,6 +14,10 @@ chip northbridge/intel/haswell
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
+ register "ec_present" = "true"
+
+ register "usb_xhci_on_resume" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index 47bcb477f5..7f08a58aca 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -49,8 +49,5 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
- pei_data->usb_xhci_on_resume = 1;
-
variant_romstage_entry(pei_data);
}
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 564177553d..192751707a 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -51,8 +51,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index e18f72b250..58f0ca82a1 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -11,6 +11,7 @@ chip northbridge/intel/haswell
register "gpu_panel_power_down_delay" = "500"
register "gpu_panel_power_up_delay" = "2000"
register "gpu_pch_backlight_pwm_hz" = "220"
+ register "ec_present" = "true"
device cpu_cluster 0x0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 8c2c5b643d..3e5cc0d65d 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -48,8 +48,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 036a89c805..c9f1027e30 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -27,8 +27,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_INTERNAL },