diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/eve/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/eve/mainboard.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/eve/ramstage.c | 23 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/mainboard.c | 48 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/ramstage.c | 69 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/mainboard.c | 14 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/ramstage.c | 8 |
8 files changed, 70 insertions, 102 deletions
diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index d853404a45..d137f92b2d 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c -ramstage-y += ramstage.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c smm-y += smihandler.c diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 9b9ccdd05f..aceb7b7f6d 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -21,6 +21,8 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/nhlt.h> +#include "gpio.h" + #define SUBSYSTEM_ID 0x1AE0006B static const char *oem_id_maxim = "GOOGLE"; @@ -74,6 +76,12 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +static void mainboard_chip_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/eve/ramstage.c b/src/mainboard/google/eve/ramstage.c deleted file mode 100644 index be3676a1f2..0000000000 --- a/src/mainboard/google/eve/ramstage.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/ramstage.h> -#include "gpio.h" - -void mainboard_silicon_init_params(FSP_SIL_UPD *params) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 5514090d4e..3e030c3270 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 89e692741e..6a7d452942 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <chip.h> +#include <delay.h> #include <device/device.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> @@ -26,8 +27,11 @@ #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <string.h> +#include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> + #define FIZZ_SKU_ID_I7_U42 0x4 #define FIZZ_SKU_ID_I5_U42 0x5 #define FIZZ_SKU_ID_I3_U42 0x6 @@ -230,6 +234,50 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + gpio_input(gpio); + + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + static const long display_timeout_ms = 3000; + + /* This is reconfigured back to whatever FSP-S expects by + gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c deleted file mode 100644 index d42f68cad4..0000000000 --- a/src/mainboard/google/fizz/ramstage.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <bootmode.h> -#include <console/console.h> -#include <delay.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <soc/ramstage.h> -#include <timer.h> - -#include <variant/gpio.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - gpio_input(gpio); - - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -void mainboard_silicon_init_params(FSP_SIL_UPD *params) -{ - const struct pad_config *pads; - size_t num; - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index b3e91e888e..5aa45d40a8 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -21,6 +21,8 @@ #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -62,6 +64,18 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + pads = variant_sku_gpio_table(&num); + gpio_configure_pads(pads, num); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c index e39afecb9c..29a83df69b 100644 --- a/src/mainboard/google/poppy/ramstage.c +++ b/src/mainboard/google/poppy/ramstage.c @@ -16,17 +16,9 @@ #include <baseboard/variants.h> #include <soc/ramstage.h> -#include <variant/gpio.h> - void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - const struct pad_config *pads; - size_t num; variant_devtree_update(); - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); - pads = variant_sku_gpio_table(&num); - gpio_configure_pads(pads, num); } void __weak variant_devtree_update(void) |