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-rw-r--r--src/mainboard/aopen/dxplplusu/romstage.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index 75aad28093..f95c7f91e2 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -21,7 +21,6 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
-#include <timestamp.h>
#include <southbridge/intel/i82801dx/i82801dx.h>
#include <northbridge/intel/e7505/raminit.h>
@@ -47,9 +46,6 @@ void mainboard_romstage_entry(unsigned long bist)
},
};
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
/* Get the serial port running and print a welcome banner */
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
@@ -61,15 +57,11 @@ void mainboard_romstage_entry(unsigned long bist)
if (!e7505_mch_is_ready()) {
enable_smbus();
- timestamp_add_now(TS_BEFORE_INITRAM);
-
/* The real MCH initialisation. */
e7505_mch_init(memctrl);
/* Hook for post ECC scrub settings and debug. */
e7505_mch_done(memctrl);
-
- timestamp_add_now(TS_AFTER_INITRAM);
}
printk(BIOS_DEBUG, "SDRAM is up.\n");