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-rw-r--r--src/mainboard/asus/kgpe-d16/devicetree.cb1
-rw-r--r--src/mainboard/asus/kgpe-d16/romstage.c2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
index ef7277d1d7..014a35f2f4 100644
--- a/src/mainboard/asus/kgpe-d16/devicetree.cb
+++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
chip southbridge/amd/sr5650 # Primary southbridge
device pci 0.0 on end # HT Root Complex 0x9600
device pci 0.1 on end # CLKCONFIG
+ device pci 0.2 on end # IOMMU
device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0)
# Slot # PCI E 1 / PCI E 2
end
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 6503b90343..ccb85f4044 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -458,6 +458,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
die("After soft_reset_x - shouldn't see this message!!!\n");
}
+ sr5650_htinit_dect_and_enable_isochronous_link();
+
/* Set default DDR memory voltage
* This will be overridden later during RAM initialization
*/