summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb8
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb8
-rw-r--r--src/mainboard/google/reef/variants/coral/devicetree.cb8
-rw-r--r--src/mainboard/google/reef/variants/pyro/devicetree.cb8
-rw-r--r--src/mainboard/google/reef/variants/sand/devicetree.cb8
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb8
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb6
7 files changed, 34 insertions, 20 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 9253f11372..80e4873694 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -42,12 +42,14 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_N_63_32"
- # PL1 override 10000 mW: Due to error in the energy calculation for
+ # PL1 override 10 W: Due to error in the energy calculation for
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 10W.
- register "tdp_pl1_override_mw" = "10000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 15,
+ }"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index cbc2e22d37..4c35bd25da 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index 00e63bc94c..f987e1da02 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index f62af8a39a..1282edb9ba 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index b62704a8f5..ad76a9194d 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -49,12 +49,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 7189508d18..a82400ff60 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 361a4a30b8..75d69d309a 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -56,9 +56,11 @@ chip soc/intel/apollolake
register "dptf_enable" = "1"
# PL1 override: 7.5W setting gives a run-time 6W actual
- register "tdp_pl1_override_mw" = "7500"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"