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-rw-r--r--src/mainboard/google/rambi/Kconfig1
-rw-r--r--src/mainboard/google/rambi/acpi/dptf.asl21
-rw-r--r--src/mainboard/google/rambi/devicetree.cb6
-rw-r--r--src/mainboard/google/rambi/mainboard.c8
4 files changed, 31 insertions, 5 deletions
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index f784aedae7..e3f5befeb2 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select ALWAYS_LOAD_OPROM
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl
index 975c9396f1..507b7c686f 100644
--- a/src/mainboard/google/rambi/acpi/dptf.asl
+++ b/src/mainboard/google/rambi/acpi/dptf.asl
@@ -49,5 +49,26 @@ Name (DTRT, Package () {
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
+Name (MPPC, Package ()
+{
+ 0x2, // Revision
+ Package () { // Power Limit 1
+ 0, // PowerLimitIndex, 0 for Power Limit 1
+ 1600, // PowerLimitMinimum
+ 6200, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 200 // StepSize
+ },
+ Package () { // Power Limit 2
+ 1, // PowerLimitIndex, 1 for Power Limit 2
+ 8000, // PowerLimitMinimum
+ 8000, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 1000 // StepSize
+ }
+})
+
/* Include Baytrail DPTF */
#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 95b2b3a398..5d9eec535e 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -32,8 +32,12 @@ chip soc/intel/baytrail
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
- register "scc_acpi_mode" = "1"
+ register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
+ register "scc_acpi_mode" = "1"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_hotplug" = "6" # 6ms Pulse
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index f8c80aef9d..19579fb0b7 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -67,15 +67,15 @@ static int int15_handler(void)
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = TV (eDP) *
- * bit 2 = EFP *
+ * bit 2 = EFP
* bit 3 = LFP
* bit 4 = CRT2
- * bit 5 = TV2 (eDP) *
- * bit 6 = EFP2 *
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
* bit 7 = LFP2
*/
X86_AX = 0x005f;
- X86_CX = 0x0006;
+ X86_CX = 0x0002;
res = 1;
break;
case 0x5f51: