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-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb4
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0bd2efc92c..61b16e65f1 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -153,7 +153,9 @@ chip soc/intel/skylake
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
- register PcieRpAdvancedErrorReporting[0] = "1"
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ # RP 1, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index ee9c5b7780..fa16ae02e5 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -153,7 +153,9 @@ chip soc/intel/skylake
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
- register PcieRpAdvancedErrorReporting[0] = "1"
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ # RP 1, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port