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-rw-r--r--src/mainboard/google/fizz/devicetree.cb30
1 files changed, 28 insertions, 2 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 3b084ff1f9..5eeb03c648 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -228,6 +228,32 @@ chip soc/intel/skylake
# RP 9 uses uses CLK SRC 2
register "PcieRpClkSrcNumber[8]" = "2"
+ # Enable Root port 11 for BtoB.
+ register "PcieRpEnable[10]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[10]" = "1"
+ # RP 11 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[10]" = "2"
+ # RP 11, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[10]" = "1"
+ # RP 11, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[10]" = "1"
+ # RP 11 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[10]" = "2"
+
+ # Enable Root port 12 for BtoB.
+ register "PcieRpEnable[11]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[11]" = "1"
+ # RP 12 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[11]" = "2"
+ # RP 12, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[11]" = "1"
+ # RP 12, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[11]" = "1"
+ # RP 12 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[11]" = "2"
+
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
@@ -351,8 +377,8 @@ chip soc/intel/skylake
end
end # PCI Express Port 9 for BtoB
device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.2 on end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on