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-rw-r--r--src/mainboard/amd/bettong/romstage.c1
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c5
-rw-r--r--src/mainboard/amd/lamar/romstage.c4
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c5
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c5
5 files changed, 13 insertions, 7 deletions
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index c3e2aa4b62..6b12afc83b 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void *resume_backup_memory;
#endif
+ /* Must come first to enable PCI MMCONF. */
amd_initmmio();
hudson_lpc_port80();
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 5c7796f915..79cc0f9a42 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index f0845821aa..58c6e42e39 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -52,7 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
hudson_lpc_decode();
outb(0x24, 0xCD6);
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6d1e4ea31f..534a8e5d49 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index e45464e39d..5deeaa8eda 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -52,8 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {