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-rw-r--r--src/mainboard/amd/dbm690t/mainboard.c7
-rw-r--r--src/mainboard/amd/mahogany/mainboard.c8
-rw-r--r--src/mainboard/amd/mahogany_fam10/mainboard.c8
-rw-r--r--src/mainboard/amd/pistachio/mainboard.c8
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c5
-rw-r--r--src/mainboard/asrock/939a785gmh/get_bus_conf.c2
-rw-r--r--src/mainboard/asrock/939a785gmh/mainboard.c8
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c15
-rw-r--r--src/mainboard/asus/m2v-mx_se/mainboard.c3
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c30
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c15
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c22
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c9
-rw-r--r--src/mainboard/intel/eagleheights/debug.c77
-rw-r--r--src/mainboard/iwill/dk8_htx/romstage.c6
-rw-r--r--src/mainboard/iwill/dk8s2/romstage.c6
-rw-r--r--src/mainboard/iwill/dk8x/romstage.c6
-rw-r--r--src/mainboard/kontron/kt690/mainboard.c5
-rw-r--r--src/mainboard/msi/ms7260/romstage.c15
-rw-r--r--src/mainboard/msi/ms9185/romstage.c14
-rw-r--r--src/mainboard/msi/ms9282/romstage.c9
-rw-r--r--src/mainboard/nvidia/l1_2pvv/get_bus_conf.c3
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c11
-rw-r--r--src/mainboard/olpc/btest/mainboard.c2
-rw-r--r--src/mainboard/sunw/ultra40/get_bus_conf.c1
-rw-r--r--src/mainboard/sunw/ultra40/irq_tables.c1
-rw-r--r--src/mainboard/sunw/ultra40/mptable.c3
-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c13
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c15
-rw-r--r--src/mainboard/technexion/tim5690/mainboard.c11
-rw-r--r--src/mainboard/technexion/tim5690/vgabios.c1
-rw-r--r--src/mainboard/technexion/tim8690/mainboard.c7
-rw-r--r--src/mainboard/tyan/s2735/romstage.c1
-rw-r--r--src/mainboard/tyan/s2912/romstage.c15
-rw-r--r--src/mainboard/via/epia-m700/Makefile.inc5
-rw-r--r--src/mainboard/via/epia-m700/wakeup.c23
-rw-r--r--src/mainboard/via/epia-n/mainboard.c2
37 files changed, 81 insertions, 311 deletions
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index dfee7c0479..2f54bfdc68 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <../southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 44752f1e91..0aea2c65ea 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <arch/coreboot_tables.h>
-#include <../southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 82a9b9eeef..c877914f86 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <arch/coreboot_tables.h>
-#include <../southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index be36458204..d1d9a849fc 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <../southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7475_ADDRESS 0x2E
@@ -35,9 +34,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
-
#define ADT7475_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
#define ADT7475_write_byte(address, val) \
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 9b482e4578..00d4b3b21a 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -101,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
/* tyan does not want the default */
diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
index e3c7acd226..43558ac984 100644
--- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c
+++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
@@ -63,8 +63,6 @@ u32 sbdn_sb700;
static u32 get_bus_conf_done = 0;
-void get_bus_conf(void);
-
void get_bus_conf(void)
{
u32 apicid_base;
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 44752f1e91..0aea2c65ea 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <arch/coreboot_tables.h>
-#include <../southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1b7c99a079..c748498fb7 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -105,10 +105,11 @@ void soft_reset(void)
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
+
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/via/k8t890/k8t890_early_car.c"
@@ -126,7 +127,7 @@ unsigned int get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
-void sio_init(void)
+static void sio_init(void)
{
u8 reg;
@@ -171,17 +172,17 @@ void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
- struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index 4d53091882..4b6f322498 100644
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -21,9 +21,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <boot/tables.h>
-#include <arch/coreboot_tables.h>
-#include "chip.h"
#include <southbridge/via/k8t890/k8t890.h>
+#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index e2c5ba5b94..3ece7aa22b 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -70,10 +70,6 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -83,18 +79,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-void activate_spd_rom(const struct mem_controller *ctrl)
+static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "southbridge/via/k8t890/k8t890_early_car.c"
+
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
+
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -144,34 +142,21 @@ unsigned int get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
-void sio_init(void)
-{
-
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- real_main(bist, cpu_init_detectedx);
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- sio_init();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
@@ -234,7 +219,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
- memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 87dd253c5a..18bebc6d76 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -86,10 +86,6 @@
#include "southbridge/sis/sis966/sis966_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -105,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -165,12 +158,12 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
+ // Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
@@ -275,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sis_init_stage1();
enable_smbus();
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 732d9f95a7..45ad9f9358 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -84,10 +84,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -103,12 +99,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -132,8 +125,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -145,8 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
-
- unsigned value;
uint32_t dword;
uint8_t byte;
@@ -166,15 +155,16 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
+ // Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
};
- struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -289,8 +279,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 43f9e7f285..218304e2f5 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -107,16 +107,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
-//#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
//first node
@@ -212,8 +207,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- //setup_mp_resource_map();
-
uart_init();
/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
index 9aec7aa65e..f9d218d6aa 100644
--- a/src/mainboard/intel/eagleheights/debug.c
+++ b/src/mainboard/intel/eagleheights/debug.c
@@ -38,7 +38,7 @@ static void print_reg(unsigned char index)
return;
}
-static void xbus_en(void)
+static inline void xbus_en(void)
{
/* select the XBUS function in the SIO */
outb(0x07, 0x2e);
@@ -66,7 +66,7 @@ static void setup_func(unsigned char func)
return;
}
-static void siodump(void)
+static inline void siodump(void)
{
int i;
unsigned char data;
@@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev)
print_debug_hex8((dev >> 8) & 7);
}
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@@ -161,7 +161,7 @@ static void print_pci_devices(void)
}
}
-static void dump_pci_device(unsigned dev)
+static inline void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
@@ -182,7 +182,7 @@ static void dump_pci_device(unsigned dev)
}
}
-static void dump_bar14(unsigned dev)
+static inline void dump_bar14(unsigned dev)
{
int i;
unsigned long bar;
@@ -227,70 +227,7 @@ static void dump_pci_devices(void)
}
}
-#if 0
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
- int i;
- print_debug("\n");
- for(i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl->channel0[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- device = ctrl->channel1[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- }
-}
-#endif
-
-void dump_spd_registers(void)
+static inline void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
@@ -322,7 +259,7 @@ void dump_spd_registers(void)
}
}
-void dump_ipmi_registers(void)
+static inline void dump_ipmi_registers(void)
{
unsigned device;
device = 0x42;
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index c34b2830f4..bddc5be7b0 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
-
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 8f9e4f488a..8dc9dc0049 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
-
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 8f9e4f488a..8dc9dc0049 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
-
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index 2ae24df15d..2e0c8e7755 100644
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -21,8 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
@@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 25cde26dcb..9f84911b36 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -83,7 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void) {}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@@ -93,10 +92,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
+
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -144,16 +144,17 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
- struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -252,8 +253,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
- memreset_setup();
-
/* Do we need apci timer, tsc...., only debug need it for better output */
/* All AP stopped? */
// init_timer(); /* Need to use TMICT to synconize FID/VID. */
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 10135a5c50..bd1c4a1189 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -71,9 +71,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-static void memreset_setup(void)
-{
-}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@@ -104,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
/* msi does not want the default */
@@ -129,7 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -144,12 +137,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
-#endif
-
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
@@ -278,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 83f894a965..c3702084e5 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -68,9 +68,6 @@
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@@ -103,9 +100,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
/* msi does not want the default */
@@ -228,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
- memreset_setup();
-
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index 838373ace3..e5380d77b8 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -92,11 +92,9 @@ static unsigned get_hcid(unsigned i)
void get_bus_conf(void)
{
-
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
int i, j;
if (get_bus_conf_done)
@@ -160,5 +158,4 @@ void get_bus_conf(void)
#endif
m->apicid_mcp55 = apicid_base+0;
m->apicid_mcp55b = apicid_base+1;
-
}
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 78afa3999d..58bf5c2958 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -83,10 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -274,8 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/olpc/btest/mainboard.c b/src/mainboard/olpc/btest/mainboard.c
index 10c6e79f1f..b184a566d0 100644
--- a/src/mainboard/olpc/btest/mainboard.c
+++ b/src/mainboard/olpc/btest/mainboard.c
@@ -69,7 +69,7 @@ static void init_dcon(void) {
write_bit(rev > 0 ? 1 : 0);
}
-void
+static void
init_cafe_irq(void){
const unsigned char slots_cafe[4] = {11, 0, 0, 0};
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index 2860ff496a..53162da97f 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -7,6 +7,7 @@
#include <cpu/amd/multicore.h>
#endif
#include <stdlib.h>
+#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c
index 10ecb4e27a..2bbbe7b110 100644
--- a/src/mainboard/sunw/ultra40/irq_tables.c
+++ b/src/mainboard/sunw/ultra40/irq_tables.c
@@ -9,6 +9,7 @@
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 900e466050..e3b22e7523 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -3,6 +3,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
@@ -32,8 +33,6 @@ extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
-
-
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 5b158e0f56..e2e297b9ce 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -77,10 +77,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -154,12 +150,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -175,8 +168,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -340,8 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus(); /* enable in sio_setup */
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 3dc8e30ef2..28332dca5d 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -80,10 +80,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -99,12 +95,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -120,8 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -263,8 +254,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// enable_smbus(); /* enable in sio_setup */
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
@@ -272,6 +261,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 8b93cd9c8c..11bb4248e7 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -21,8 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
@@ -179,7 +178,7 @@ static void set_thermal_config(void)
}
/* Mainboard specific GPIO setup. */
-void mb_gpio_init(u16 *iobase)
+static void mb_gpio_init(u16 *iobase)
{
/* Init Super I/O GPIOs. */
it8712f_enter_conf();
@@ -193,7 +192,7 @@ void mb_gpio_init(u16 *iobase)
}
/* The LCD's panel id seletion. */
-void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
+static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
{
switch (num_id) {
case 0x1:
@@ -226,9 +225,6 @@ void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
*************************************************/
static void tim5690_enable(device_t dev)
{
- struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info;
-
rs690_vbios_regs vbios_regs;
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
u8 port2;
@@ -240,6 +236,7 @@ static void tim5690_enable(device_t dev)
/* The LCD's panel id seletion by switch. */
port2 = inb(gpio_base+1);
lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
+
/* No support TV */
vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
vgabios_init(&vbios_regs);
diff --git a/src/mainboard/technexion/tim5690/vgabios.c b/src/mainboard/technexion/tim5690/vgabios.c
index 45b11ae41c..372c4b6647 100644
--- a/src/mainboard/technexion/tim5690/vgabios.c
+++ b/src/mainboard/technexion/tim5690/vgabios.c
@@ -36,6 +36,7 @@ static void vbios_fun_init(rs690_vbios_regs *vbios_regs)
vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
}
+
/* BIOS int15 function */
int tim5690_int15_handler(struct eregs *regs)
{
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index b032483fad..294c0f2590 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <../southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index 0a74579b89..f581de431e 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -15,7 +15,6 @@
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 3b79a29153..26ce672bf4 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -83,10 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@@ -130,8 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -271,8 +262,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
- memreset_setup();
-
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
@@ -280,6 +269,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
diff --git a/src/mainboard/via/epia-m700/Makefile.inc b/src/mainboard/via/epia-m700/Makefile.inc
index da2b05f02f..761c07a300 100644
--- a/src/mainboard/via/epia-m700/Makefile.inc
+++ b/src/mainboard/via/epia-m700/Makefile.inc
@@ -19,5 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-obj-y += wakeup.o
+# This code is unused and should be replaced by the generic resume code
+# completely. If anyone works on wakeup for this chipset/board, delete
+# wakeup.c when you are done.
+# obj-y += wakeup.o
diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c
index bb232b4dfe..bae0fd4b32 100644
--- a/src/mainboard/via/epia-m700/wakeup.c
+++ b/src/mainboard/via/epia-m700/wakeup.c
@@ -19,6 +19,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+/* FIXME This code should be dropped and instead the generic resume code
+ * should be used.
+ */
+
/* Parts of this code is taken from reboot.c from Linux. */
/*
@@ -96,19 +100,6 @@ static unsigned char jump_to_wakeup[] = {
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
};
-/*
- * Switch to real mode and then execute the code
- * specified by the code and length parameters.
- * We assume that length will aways be less that 100!
- */
-static unsigned char show31[6] = {
- 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
-};
-
-static unsigned char show32[6] = {
- 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
-};
-
void acpi_jump_wake(u32 vector)
{
u32 dwEip;
@@ -337,8 +328,6 @@ void acpi_jump_wake(u32 vector)
* Enable A20 gate (return -1 on failure)
*/
-// #include "boot.h"
-
#define MAX_8042_LOOPS 100000
static int empty_8042(void)
@@ -375,13 +364,9 @@ static int a20_test(int loops)
int ok = 0;
int saved, ctr;
-// set_fs(0x0000);
-// set_gs(0xffff);
-
saved = ctr = *((u32 *) A20_TEST_ADDR);
while (loops--) {
- //wrfs32(++ctr, A20_TEST_ADDR);
*((u32 *) A20_TEST_ADDR) = ++ctr;
diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c
index 660c559020..4206b24d5d 100644
--- a/src/mainboard/via/epia-n/mainboard.c
+++ b/src/mainboard/via/epia-n/mainboard.c
@@ -23,8 +23,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <boot/tables.h>
+#include <southbridge/via/vt8237r/vt8237r.h>
#include "chip.h"
-#include "../../../southbridge/via/vt8237r/vt8237r.h"
int add_mainboard_resources(struct lb_memory *mem)
{