diff options
Diffstat (limited to 'src/mainboard')
31 files changed, 4868 insertions, 0 deletions
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 6dd34ea7df..facfde9252 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -42,6 +42,8 @@ config VENDOR_EAGLELION bool "EagleLion" config VENDOR_EMULATION bool "Emulation" +config VENDOR_GETAC + bool "Getac" config VENDOR_GIGABYTE bool "GIGABYTE" config VENDOR_HP @@ -202,6 +204,11 @@ config MAINBOARD_VENDOR config MAINBOARD_VENDOR string + default "Getac" + depends on VENDOR_GETAC + +config MAINBOARD_VENDOR + string default "GIGABYTE" depends on VENDOR_GIGABYTE @@ -404,6 +411,7 @@ source "src/mainboard/dell/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" source "src/mainboard/ibm/Kconfig" diff --git a/src/mainboard/getac/Kconfig b/src/mainboard/getac/Kconfig new file mode 100644 index 0000000000..4a4a8c06e6 --- /dev/null +++ b/src/mainboard/getac/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_GETAC + +source "src/mainboard/getac/p470/Kconfig" + +endchoice diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig new file mode 100644 index 0000000000..08030b7532 --- /dev/null +++ b/src/mainboard/getac/p470/Kconfig @@ -0,0 +1,96 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_GETAC_P470 + bool "P470" + select ARCH_X86 + select CPU_INTEL_CORE + select CPU_INTEL_SOCKET_MFCPGA478 + select NORTHBRIDGE_INTEL_I945 + select SOUTHBRIDGE_INTEL_I82801GX + select SOUTHBRIDGE_TI_PCIXX12 + select SUPERIO_SMSC_FDC37N972 + select SUPERIO_SMSC_SIO10N268 + select BOARD_HAS_FADT + select GENERATE_ACPI_TABLES + select GENERATE_PIRQ_TABLE + select GENERATE_MP_TABLE + select HAVE_HARD_RESET + select HAVE_ACPI_RESUME + select HAVE_MAINBOARD_RESOURCES + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + select AP_IN_SIPI_WAIT + select UDELAY_LAPIC + select HAVE_SMI_HANDLER + select BOARD_ROMSIZE_KB_1024 + select USE_DCACHE_RAM + select GFXUMA + select TINY_BOOTBLOCK + +config MAINBOARD_DIR + string + default getac/p470 + depends on BOARD_GETAC_P470 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_GETAC_P470 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_GETAC_P470 + +config MAINBOARD_PART_NUMBER + string + default "P470" + depends on BOARD_GETAC_P470 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + depends on BOARD_GETAC_P470 + +config IRQ_SLOT_COUNT + int + default 18 + depends on BOARD_GETAC_P470 + +config MAX_CPUS + int + default 4 + depends on BOARD_GETAC_P470 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_GETAC_P470 + +config FALLBACK_VGA_BIOS_FILE + string + default "getac-pci8086,27a2.rom" + depends on BOARD_GETAC_P470 + +config HAVE_ACPI_SLIC + bool + default y + depends on BOARD_GETAC_P470 + diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc new file mode 100644 index 0000000000..fd280d75ee --- /dev/null +++ b/src/mainboard/getac/p470/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += rtl8168.o +obj-$(CONFIG_HAVE_ACPI_SLIC) += acpi_slic.o + +smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl new file mode 100644 index 0000000000..8a69a8815b --- /dev/null +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope(\_SB) { + + Name(NIMH, "NiMH") + Name(LION, "Lion") + + Device (BAT0) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ \_SB }) + + Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) + + /* Status */ + Method(_STA, 0) + { + Sleep(120) + If(\_SB.PCI0.LPCB.EC0.BAT) { + Return(0x1f) + } Else { + Return(0x0f) + } + } + + /* Battery Info */ + Method(_BIF, 0) + { + Name(PBIF, Package() { + 0x01, + 0x0fa0, + 0x0fa0, + 0x01, + 0x2ee0, // Capacity? + 0x012c, + 0x96, + 0x01, + 0x01, + "Battery", // Name + "", // Number + "LIon", // Type + "Generic" // Vendor + }) + + // Is battery there? + Store(_STA(), Local0) + And(Local0, 0x10, Local0) + If(LNot(Local0)) { + Return (PBIF) + } + + Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1)) + Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4)) + + Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0) + Store(Local0, Index(PBIF, 2)) + + Divide(Local0, 10, Local1, Local2) + Store(Local2, Index(PBIF, 5)) + + Divide(Local0, 20, Local1, Local2) + Store(Local2, Index(PBIF, 6)) + + If(\_SB.PCI0.LPCB.EC0.BTYP) { + Store(NIMH, Index(PBIF, 11)) + } Else { + Store(LION, Index(PBIF, 11)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.BAT) { + Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) + + Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) + Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) + Divide(Local3, 0x64, Local3, Local0) + Increment(Local0) + Store(Local0, Index(PBST, 2)) + + Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3) + Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0) + And (Not (Local0), 0xFFFF, Local0) + Store (Local0, Index(PBST,1)) + + // AC Power connected? + If(\_SB.PCI0.LPCB.EC0.ADP) { + If(\_SB.PCI0.LPCB.EC0.CHRG) { + Store(2, Index(PBST, 0)) + } Else { + Store(0, Index(PBST, 0)) + } + } Else { + If(LLess(Local3, 25)) { + Store(5, Index(PBST, 0)) + } Else { + Store(1, Index(PBST, 0)) + } + } + } + Return(PBST) + } + } + + + Device (BAT1) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ \_SB }) + + Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) + + /* Status */ + Method(_STA, 0) + { + Sleep(120) + If(\_SB.PCI0.LPCB.EC0.BAT2) { + Return(0x1f) + } Else { + Return(0x0f) + } + } + + /* Battery Info */ + Method(_BIF, 0) + { + Name(PBIF, Package() { + 0x01, + 0x0fa0, + 0x0fa0, + 0x01, + 0x2ee0, // Capacity? + 0x012c, + 0x96, + 0x01, + 0x01, + "Battery", // Name + "", // Number + "LIon", // Type + "Generic" // Vendor + }) + + // Is battery there? + Store(_STA(), Local0) + And(Local0, 0x10, Local0) + If(LNot(Local0)) { + Return (PBIF) + } + + Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1)) + Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4)) + + Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0) + Store(Local0, Index(PBIF, 2)) + + Divide(Local0, 10, Local1, Local2) + Store(Local2, Index(PBIF, 5)) + + Divide(Local0, 20, Local1, Local2) + Store(Local2, Index(PBIF, 6)) + + If(\_SB.PCI0.LPCB.EC0.BTY2) { + Store(NIMH, Index(PBIF, 11)) + } Else { + Store(LION, Index(PBIF, 11)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.BAT2) { + Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) + + Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) + Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) + Divide(Local3, 0x64, Local3, Local0) + Increment(Local0) + Store(Local0, Index(PBST, 2)) + + Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3) + Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0) + And (Not (Local0), 0xFFFF, Local0) + Store (Local0, Index(PBST,1)) + + // AC Power connected? + If(\_SB.PCI0.LPCB.EC0.ADP) { + If(\_SB.PCI0.LPCB.EC0.CRG2) { + Store(2, Index(PBST, 0)) + } Else { + Store(0, Index(PBST, 0)) + } + } Else { + If(LLess(Local3, 25)) { + Store(5, Index(PBST, 0)) + } Else { + Store(1, Index(PBST, 0)) + } + } + } + Return(PBST) + } + } + + Name (PWRS, 0) + Name (ACFG, 0) + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (ACST, 0x00) + Method (_PSR, 0) + { + If(ACFG) { + Store(ACST, Local0) + } Else { + Store(\_SB.PCI0.LPCB.EC0.ADP, Local0) + Store(Local0, ACST) + Store(1, ACFG) + } + Sleep(120) + Return (Local0) + } + + Name(_PCL, Package(){ + \_SB, + BAT0, + BAT1 + }) + } +} diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl new file mode 100644 index 0000000000..30e78fad2a --- /dev/null +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -0,0 +1,675 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x37) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + MODE, 1, // Thermal Policy (Quiet/Perform) + FAN, 1, // Fan Power (On/Off) + LIDS, 1, // LID Status (0=Open/1=Close) + LSW0, 1, // LCD Power Switch + + BTYP, 1, // Battery Type (0=LiIon/1=NiMh) + MWKE, 1, // Enable Wakeup from RI + ADP, 1, // AC Adapter (0=Offline/1=Online) + BAT, 1, // Battery (0=Not Present/1=Present) + SLPT, 3, // Set Sleep Type on SLP enter (1=S1...4=S4) + CHRG, 1, // 0=Battery not charging/1=Battery charging + RI_W, 1, // Wake-up event source is RI + KB_W, 1, // Wake-up event source is keyboard + BATW, 1, // Wake-up event source is Battery Low + PMEW, 1, // Wake-up event source is PME + + // Battery 0 Registers + // Battery Life = BRC0/BPR0 + // Battery percentage = BRC0/BFC0 * 100 + BDC0, 16, // Designed Capacity + BFC0, 16, // Last Full Charge Capacity + BDV0, 16, // Design Voltage + BPR0, 16, // Battery Present Rate + BRC0, 16, // Battery Remaining Capacity + BPV0, 16, // Battery Present Voltage + + Offset(0x11), + CTMP, 8, // CPU Temperature + Offset(0x15), + CTRO, 8, // EC throttling on trip point + CRTT, 8, // Critical Shut-down Temperature + Offset(0x17), + BKLL, 8, // Backlight Level + + // Battery 2 Registers + Offset(0x20), + , 4, + BTY2, 1, // Battery Type (0=LiIon/1=NiMh) + , 2, + BAT2, 1, // Battery (0=Not Present/1=Present) + , 3, + CRG2, 1, // 0=Battery not charging/1=Battery charging + Offset(0x22), + BDC2, 16, // Designed Capacity + BFC2, 16, // Last Full Charge Capacity + BDV2, 16, // Design Voltage + BPR2, 16, // Battery Present Rate + BRC2, 16, // Battery Remaining Capacity + BPV2, 16, // Battery Present Voltage + BTP2, 16, // Trip Point + + PBMO, 2, // PBMO power control method + ECO, 1, // ECO on/off status + SUN, 1, // Sunlight Readable + RF, 1, // RF Enable/Disable status + DOCK, 1, // Dock In/Out status + CBAT, 1, // Car Battery status + APPS, 1, // OSD utility status + Offset(0x33), + ODDS, 1 + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + Return (ECMD) + } + + // EC Query methods, called upon SCI interrupts. + Method (_Q01, 0) + { + Notify (\_PR.CPU0, 0x80) + If(ADP) { + Store(1, \_SB.AC.ACST) + TRAP(0xe3) + Store(1, PWRS) + TRAP(0x2b) + } Else { + Store(0, \_SB.AC.ACST) + Notify(\_SB.AC, 0x80) + Notify(\_SB.BAT0, 0x80) + Store(0, PWRS) + TRAP(0x2b) + } + + PNOT() + } + + Method (_Q02, 0) + { + If(BAT) { + Notify(\_SB.BAT0, 0x00) + Notify(\_SB.AC, 0x80) + } Else { + Notify(\_SB.AC, 0x80) + Notify(\_SB.BAT0, 0x01) + } + + PNOT() + } + + Method (_Q05, 0) + { + Notify(SLPB, 0x80) + PNOT() + } + + Method (_Q07, 0) + { + TRAP(0xe0) + + If (LEqual(RTCF, 0x00)) { + Notify(LID0, 0x80) + } else { + TRAP(0xc1) + } + } + + Method (_Q09, 0) + { + Notify(BAT0, 0x80) + Notify(BAT1, 0x80) + } + + Method (_Q0A, 0) + { + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q20, 0) + { + Notify(\_SB.ECO, 0x81) + } + + Method (_Q21, 0) + { + Notify(\_SB.ECO, 0x82) + } + + Method (_Q22, 0) + { + Notify(\_SB.ECO, 0x83) + } + + Method (_Q23, 0) + { + Notify(\_SB.ECO, 0x84) + } + + Method (_Q24, 0) + { + Store(0x3f, HOTK) + If(IGDS) { + HKDS(10) + } Else { + TRAP(0xE1) + } + Notify (\_SB.ECO, 0x85) + } + + Method (_Q25, 0) + { + Store(0x40, HOTK) + TRAP(0xe1) + Notify(\_SB.ECO, 0x86) + } + + Method (_Q26, 0) + { + Store(0x41, HOTK) + TRAP(0xe1) + Notify(\_SB.ECO, 0x87) + } + + Method (_Q27, 0) + { + Notify(\_SB.ECO, 0x88) + } + + Method (_Q28, 0) + { + Notify(\_SB.ECO, 0x89) + } + + Method (_Q29, 0) + { + Notify(\_SB.ECO, 0x8a) + } + + Method (_Q2A, 0) + { + Store(0x57, HOTK) + TRAP(0xe1) + Notify(\_SB.ECO, 0x8b) + } + + Method (_Q2B, 0) + { + Notify(SLPB, 0x80) + Notify(\_SB.ECO, 0x8c) + } + + Method (_Q2C, 0) + { + Store(0x59, HOTK) + TRAP(0xe1) + } + + Method (_Q38, 0) + { + // IDE TODO + } + + Method (_Q39, 0) + { + // SATA TODO + } + + Method (_Q3A, 0) + { + Store(1, BRTL) + Notify(\_SB.ECO, 0x93) + } + + Method (_Q3B, 0) + { + Store(0, BRTL) + Notify(\_SB.ECO, 0x93) + } + + Method (_Q3C, 0) + { + Store(1, SUN) + Notify(\_SB.ECO, 0x92) + } + + Method (_Q3D, 0) + { + Store(0, SUN) + Notify(\_SB.ECO, 0x92) + } + + /* Enable RF device */ + Method (_Q3E, 0) + { + TRAP(0xdf) + } + + /* Disable RF device */ + Method (_Q3F, 0) + { + TRAP(0xc0) + } + + /* ACBS LAN Power On */ + Method (_Q40, 0) + { + TRAP(0xd0) + Sleep(500) + Notify(RP04, 0) + } + + /* ACBS LAN Power Off */ + Method (_Q41, 0) + { + TRAP(0xd1) + } + + Method (_Q42, 0) + { + TRAP(0xf3) + } + + Method (_Q43, 0) + { + TRAP(0xf4) + } + + Method (_Q48, 0) + { + TRAP(0xd2) // Check AC Status + Store (1, ODDS) + Notify(\_SB.ECO, 0x90) + } + + Method (_Q49, 0) + { + TRAP(0xd2) // Check AC Status + Store (0, ODDS) + Notify(\_SB.ECO, 0x90) + } + + + Method (_Q4C, 0) + { + Notify(\_SB.ECO, 0x94) + } + + Method (_Q4D, 0) + { + Notify(\_SB.ECO, 0x95) + } + + Method (_Q4E, 0) + { + // PATA TODO + } + + Method (_Q4F, 0) + { + TRAP(0xf9) + Notify(\_SB.ECO, 0x95) + } + + Method (_Q5C, 0) + { + // Store(2, IGPS) + Notify(\_SB.ECO, 0x94) + } + + Method (_Q70, 0) + { + Notify(\_SB.ECO, 0x96) + } + + Method (_Q71, 0) + { + Notify(\_SB.ECO, 0x97) + } + + // TODO Scope _SB devices for AC power, LID, Power button +} + +Scope(\_SB) +{ + /* This device is used by the GETAC P470 Windows drivers. */ + + Device (ECO) + { + Name(_HID, "MTC0303") // MTC0303 BIOS Service Provider + Method (GDPD, 0, Serialized) + { + // Set flag byte to zero + Store (0, Local0) + + If (And(BRTL, 0x01)) { + Or(Local0, 0x01, Local0) + } + + If (And(BRTL, 0x02)) { + Or(Local0, 0x04, Local0) + } + + If (And(BRTL, 0x04)) { + Or(Local0, 0x02, Local0) + } + + If (And(BRTL, 0x30)) { + Or(Local0, 0x10, Local0) + } + + If (And(BRTL, 0x40)) { + Or(Local0, 0x40, Local0) + } + + Return (Local0) + } + + Method (GDPC, 0, Serialized) + { + Store (0, Local0) + + If (And(BRTL, 0x10)) { + Or(Local0, 0x04, Local0) + } + + If (And( BRTL, 0x20)) { + Or(Local0, 0x01, Local0) + } + + If (And(BRTL, 0x40)) { + Or(Local0, 0x02, Local0) + } + + Return (Local0) + } + + /* Set Brightness Level */ + Method(SBLL, 1, Serialized) + { + Store (Arg0, BRTL) + TRAP(0xd5) // See mainboard_smi.c + Return (0) + } + + /* Get Brightness Level */ + Method(GBLL, 0, Serialized) + { + TRAP(0xd6) // See mainboard_smi.c + Return (BRTL) + } + + /* Get Brightness Level Medium? */ + Method(GBLM, 0, Serialized) + { + Store(0x3f, BRTL) + // XXX don't we have to set the brightness? + Return(BRTL) + } + + /* ??? */ + Method(SUTE, 1, Serialized) + { + If (And(Arg0, 0x01)) { + TRAP(0xf5) + } Else { + TRAP(0xf6) + } + Return (0) + } + + /* ??? */ + Method(GECO, 0, Serialized) + { + TRAP(0xd7) + Return (ODDS) + } + + /* ??? */ + Method(GBSL, 0, Serialized) + { + TRAP(0xd8) + Return (BRTL) + } + + /* ??? Get LED/Device Enable Status */ + Method(GRFD, 0, Serialized) + { + /* Let coreboot update the flags */ + TRAP(0xe5) + + Store (0, Local0) + If(And(RFDV, 0x01)) { + Or(Local0, 0x01, Local0) + } + If(And(RFDV, 0x02)) { + Or(Local0, 0x02, Local0) + } + If(And(RFDV, 0x02)) { + Or(Local0, 0x02, Local0) + } + If(And(RFDV, 0x04)) { + Or(Local0, 0x04, Local0) + } + If(And(RFDV, 0x08)) { + Or(Local0, 0x08, Local0) + } + If(And(GP16, 0x01)) { // GDIS + Or(Local0, 0x10, Local0) + } + If(And(GP13, 0x01)) { // WIFI Led (WLED) + Or(Local0, 0x20, Local0) + } + If(And(BTEN, 0x01)) { // BlueTooth Enable + Or(Local0, 0x40, Local0) + } + If(And(GP11, 0x01)) { // GPS Enable + Or(Local0, 0x80, Local0) + } + + Return (Local0) + } + + /* Set RFD */ + Method(SRFD, 1, Serialized) + { + If (And(Arg0, 0x01)) { + Store (1, GP15) // GLED + Store (1, GP16) // GDIS + } Else { + Store (0, GP15) + Store (0, GP16) + } + + /* WIFI */ + If (And(Arg0, 0x02)) { + Store (1, GP13) // WLED + Store (1, GP26) // WLAN + } Else { + Store (0, GP13) + Store (0, GP26) + } + + /* Bluetooth */ + If (And(Arg0, 0x04)) { + Store (1, GP14) // BLED + Store (1, BTEN) + } Else { + Store (0, GP14) // BLED + Store (0, BTEN) + } + Return (0) + } + + /* Get DKD */ + Method(GDKD, 0, Serialized) + { + TRAP(0xd9) + Return (BRTL) + } + + /* Set DKD */ + Method(SDKD, 1, Serialized) + { + TRAP(0xda) + Return (0) + } + + /* Set IGD (Graphics) */ + Method(SIGD, 1, Serialized) + { + If (And(Arg0, 0x01)) { + TRAP(0xf7) + } Else { + TRAP(0xf8) + } + Return (0) + } + + /* SMI-C? Set Mic? */ + Method (SMIC, 1, Serialized) + { + If (And(Arg0, 0x01)) { + TRAP(0xeb) + } Else { + TRAP(0xec) + } + Return (0) + } + + /* ??? */ + Method(GTSD, 0, Serialized) + { + Return (GP20) // TSDT + } + + /* Not even decent function names anymore? */ + Method(S024, 1, Serialized) + { + If (And(Arg0, 0x01)) { + TRAP(0xf1) + } Else { + TRAP(0xf2) + } + Return (0) + } + + /* Get CVD */ + Method(GCVD, 0, Serialized) + { + TRAP(0xf9) + Return (BRTL) + } + + /* ??? Something with PATA */ + Method(S025, 1, Serialized) + { + If(And(Arg0, 0x01)) { + TRAP(0xfc) + + Store (1, GP33) // CREN + Sleep(1500) + + Store (1, GP34) // CRRS + Sleep(500) + + Notify(^^PCI0.PATA, 0) + Notify(^^PCI0.PATA.PRID, 0) + } Else { + TRAP(0xfb) + Sleep(1500) + Store(0, GP33) // CREN + Sleep(1500) + Notify(^^PCI0.PATA, 0) + Notify(^^PCI0.PATA.PRID, 0) + Notify(^^PCI0.PATA.PRID.DSK1, 1) + Notify(^^PCI0.PATA.PRID.DSK0, 1) + } + Return (0) + } + + /* ??? */ + Method(G021, 0, Serialized) + { + TRAP(0xfe) + If (LEqual(ACIN, 0)) { + TRAP(0xfa) + TRAP(0xfd) + If (LEqual(ODDS, 1)) { + TRAP(0xfb) + Notify(^^PCI0.PATA, 0) + Notify(^^PCI0.PATA.PRID.DSK1, 1) + Notify(^^PCI0.PATA.PRID.DSK0, 1) + Sleep (1500) + Store (0, GP33) // CREN + Sleep (1500) + Notify(^^PCI0.PATA, 0) + Notify(^^PCI0.PATA.PRID.DSK1, 1) + Notify(^^PCI0.PATA.PRID.DSK0, 1) + Return (0) + } + } + /* All Else Cases */ + Notify(ECO, 0xb1) + Return (1) + } + + /* Get RFS */ + Method(GRFS, 0, Serialized) + { + TRAP(0xff) + Return(BRTL) + } + + /* ??? */ + Method(S00B, 1, Serialized) + { + If (And(Arg0, 1)) { + TRAP(0xdc) + } Else { + TRAP(0xdd) + } + Return (0) + } + + + + } +} diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl new file mode 100644 index 0000000000..7dc18c8211 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x2C. + */ + + // Hot Plug + Method (_L01, 0) + { + // TODO + } + + // Software GPE + Method (_L02, 0) + { + Store (0, GPEC) + } + + // USB1 + Method (_L03, 0) + { + Notify (\_SB.PCI0.USB1, 2) + } + + // USB2 + Method (_L04, 0) + { + Notify (\_SB.PCI0.USB2, 2) + } + + // AC97 + Method (_L05, 0) + { + Notify (\_SB.PCI0.MODM, 2) + Notify (\_SB.PCI0.HDEF, 2) + } + + // _L06 TCOSCI + + // SMBus (Reserved!) + Method (_L07, 0) + { + Store (0x20, \_SB.PCI0.SBUS.HSTS) + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + // Don't care + } + + // PCIe + Method (_L09, 0) + { + // TODO + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + Notify (\_SB.PCI0.PCIB.LANR, 0x02) + } + + // USB3 + Method (_L0C, 0) + { + Notify(\_SB.PCI0.USB3, 2) + } + + // PME B0 + Method (_L0D, 0) + { + Notify(\_SB.PCI0.EHC1, 2) + } + + // USB4 + Method (_L0E, 0) + { + Notify(\_SB.PCI0.USB4, 2) + } +} diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000000..c78d7d6248 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Network + Package() { 0x0007ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 16 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 22 }, + Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Network 0:7.0 + Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + } +} + diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..28b06a1e3e --- /dev/null +++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0005ffff, 0, 0, 16}, + Package() { 0x0005ffff, 1, 0, 17}, + Package() { 0x0005ffff, 2, 0, 18}, + Package() { 0x0005ffff, 4, 0, 19} // ?? 4 ?? + }) +} Else { + Return (Package() { + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 4, \_SB.PCI0.LPCB.LNKD, 0}, // Really 4?? + }) +} + diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl new file mode 100644 index 0000000000..88ff8b4ea7 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/mainboard.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LID0) +{ + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + If(\_SB.PCI0.LPCB.EC0.LIDS) { + Return (0) + } Else { + Return (1) + } + } +} + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +#include "acpi/battery.asl" diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl new file mode 100644 index 0000000000..eeaded838f --- /dev/null +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* SMI Function Trap */ +OperationRegion(SMI1, SystemMemory, 0xC0DEDEAD, 0x100) +Field(SMI1, AnyAcc, NoLock, Preserve) +{ + BCMD, 8, + DID, 32, + INFO, 1024 +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + TRAP(0xed) + Sleep(1000) + + Store(0, \_SB.ACFG) + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + Store (0x4c, BCMD) + } + + // Are we going to S4? + If (Lequal(Arg0, 4)) { + TRAP(0xe7) + TRAP(0xea) + } + + // Are we going to S5? + If (Lequal(Arg0, 5)) { + Store (0x4b, BCMD) + TRAP(0xde) + } + + // The 2.6.12.5 ACPI engine seems to optimize the + // If(LEqual(Arg0, 5)) path away. This keeps it from doing so: + TRAP(Arg0) + Store(Arg0, DBG0) + // End of ugly OS bug workaround +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // Enable GPS + Store (1, GP11) // GPSE + + // Wake from S3 or S4? + If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) { + If (And(CFGD, 0x01000000)) { + If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) { + TRAP(0x3d) + } + } + } + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + If (LEqual(RP1D, 0)) { + Notify(\_SB.PCI0.RP01, 0) + } + + If (LEqual(RP3D, 0)) { + Notify(\_SB.PCI0.RP03, 0) + } + + If (LEqual(RP4D, 0)) { + Notify(\_SB.PCI0.RP04, 0) + } + + // Are we coming from S3? + If (LEqual(Arg0, 3)) { + TRAP(0xeb) + TRAP(0x46) + } + + // Are we coming from S4? + If (LEqual(Arg0, 4)) { + Notify(SLPB, 0x02) + If (DTSE) { + TRAP(0x47) + } + } + + // Windows XP SP2 P-State restore + If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { + If (LGreater(\_PR.CPU0._PPC, 0)) { + Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + PNOT() + Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + PNOT() + } Else { + Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + PNOT() + Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + PNOT() + } + } + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CPU0._PPC) +External (\_PR_.CPU1._PPC) +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } + + // Notify the Batteries + Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST + Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST +} + +// Hardcoded for now.. +Name (CFGD, 0x113B69F1) + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + If (DTSE) { + TRAP(0x47) + } + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + TRAP(0x3d) + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) + + /* OS Init */ + TRAP(0x32) + } +} + diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl new file mode 100644 index 0000000000..95cd1c1ed7 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -0,0 +1,677 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* SMSC SIO10N268 */ + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + OperationRegion(SIOR, SystemIO, 0x4e, 0x02) + Field (SIOR, ByteAcc, Nolock, Preserve) + { + INDX, 8, + DATA, 8 + } + + Mutex (SIOM, 0x00) + + Method (READ, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (DATA, Local1) + Store (0xaa, INDX) + } + And (Local1, Arg2, Local1) + Release(SIOM) + Return(Local1) + } + + Method (WRIT, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (Arg2, DATA) + Store (0xaa, INDX) + } + Release(SIOM) + } + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + Acquire (SIOM, 0xffff) + + // Is the hardware enabled? + Store (READ(0, 0x24, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x08), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x24, 0x00) + + Store(READ(0, 0x28, 0x0f), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA) + IRQNoFlags(_IRA) { 4 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IOA._MIN, IOLO) + CreateByteField(RSRC, 0x03, IOHI) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IOA._MAX, IORL) + CreateByteField(RSRC, 0x05, IORH) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQL) + + Store (READ(0, 0x24, 0xff), Local0) + And (Local0, 0xc0, Local1) + ShiftRight(Local1, 0x06, Local1) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOLO) + Store(Local1, IOHI) + Store(IOLO, IORL) + Store(IOHI, IORH) + + /* Interrupt */ + Store(READ(0, 0x28, 0xf0), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQL) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x24, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + ShiftLeft(Local0, 4, Local0) + + Store(READ(0, 0x28, 0x0f), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x24, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + /* IRDA? */ + Store(READ(0, 0x0c, 0x38), Local0) + If (LNotEqual(Local0, Zero)) { + Return (0) + } + + // Is the hardware enabled? + Store (READ(0, 0x25, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x80), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x25, 0x00) + + Store(READ(0, 0x28, 0xf0), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB) + IRQNoFlags(_IRB) { 3 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IOB._MIN, IOLO) + CreateByteField(RSRC, 0x03, IOHI) + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IOB._MAX, IORL) + CreateByteField(RSRC, 0x05, IORH) + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQL) + + Store (READ(0, 0x25, 0xff), Local0) + And (Local0, 0xc0, Local1) + ShiftRight(Local1, 0x06, Local1) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOLO) + Store(Local1, IOHI) + Store(IOLO, IORL) + Store(IOHI, IORH) + + /* Interrupt */ + Store(READ(0, 0x28, 0x0f), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQL) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x25, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + + Store(READ(0, 0x28, 0xf0), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x25, Local0) + + Store(READ(0, 0x0c, 0xff), Local0) + Not(0x38, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x0c, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + + Device (UAR3) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 3) + Name(_DDN, "COM3") + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + Acquire (SIOM, 0xffff) + + // Is the hardware enabled? + Store (READ(0, 0x1b, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x02), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x1b, 0x00) + + Store(READ(0, 0x1d, 0x0f), Local0) + WRIT(0, 0x1d, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x02, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3e8, 0x3e8, 0x8, 0x8) + IRQNoFlags() { 5 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x3e8, 0x3e8, 0x8, 0x8, _IOA) + IRQNoFlags(_IRA) { 5 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IOA._MIN, IOLO) + CreateByteField(RSRC, 0x03, IOHI) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IOA._MAX, IORL) + CreateByteField(RSRC, 0x05, IORH) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQL) + + Store (READ(0, 0x1b, 0xff), Local0) + And (Local0, 0xc0, Local1) + ShiftRight(Local1, 0x06, Local1) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOLO) + Store(Local1, IOHI) + Store(IOLO, IORL) + Store(IOHI, IORH) + + /* Interrupt */ + Store(READ(0, 0x1d, 0xf0), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQL) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x1b, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + ShiftLeft(Local0, 4, Local0) + + Store(READ(0, 0x1d, 0x0f), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x1d, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x1b, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x02, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x04, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x02, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x04, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x02, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + + + Device (UAR4) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 4) + Name(_DDN, "COM4") + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + Acquire (SIOM, 0xffff) + + // Is the hardware enabled? + Store (READ(0, 0x1c, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x04), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x1c, 0x00) + + Store(READ(0, 0x1d, 0x0f), Local0) + WRIT(0, 0x1d, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x04, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2e8, 0x2e8, 0x8, 0x8) + IRQNoFlags() { 11 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x2e8, 0x2e8, 0x8, 0x8, _IOA) + IRQNoFlags(_IRA) { 11 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IOA._MIN, IOLO) + CreateByteField(RSRC, 0x03, IOHI) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IOA._MAX, IORL) + CreateByteField(RSRC, 0x05, IORH) // Why? + CreateByteField(RSRC, + \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQL) + + Store (READ(0, 0x1c, 0xff), Local0) + And (Local0, 0xc0, Local1) + ShiftRight(Local1, 0x06, Local1) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOLO) + Store(Local1, IOHI) + Store(IOLO, IORL) + Store(IOHI, IORH) + + /* Interrupt */ + Store(READ(0, 0x1d, 0xf0), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQL) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x1c, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + ShiftLeft(Local0, 4, Local0) + + Store(READ(0, 0x1d, 0x0f), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x1d, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x1c, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x04, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x08, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x04, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x04, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + +} + diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl new file mode 100644 index 0000000000..93bdbcfe66 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + // TODO These could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x00) + Name(TC2V, 0x0a) + Name(TSPV, 0x32) + + + // Convert from °C to 1/10 Kelvin + Method(DEGR, 1, NotSerialized) + { + Store(Arg0, Local0) + // 10ths of degrees + Multiply(Local0, 10, Local0) + // 0°C is 273.15 K, we need to round it. + Add(Local0, 2732, Local0) + Return(Local0) + } + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0) + Store(DEGR(Local0), Local0) + Return(Local0) + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0) + Store(DEGR(Local0), Local0) + Return(Local0) + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0) + Store(DEGR(Local0), Local0) + Return(Local0) + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU0, \_PR.CPU1}) + } + Return (Package() {\_PR.CPU0}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + } +} + diff --git a/src/mainboard/getac/p470/acpi/video.asl b/src/mainboard/getac/p470/acpi/video.asl new file mode 100644 index 0000000000..507a390d27 --- /dev/null +++ b/src/mainboard/getac/p470/acpi/video.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/getac/p470/acpi_slic.c b/src/mainboard/getac/p470/acpi_slic.c new file mode 100644 index 0000000000..5744efad90 --- /dev/null +++ b/src/mainboard/getac/p470/acpi_slic.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +static const char slic[0x4] = { + 0x53, 0x4c, 0x49, 0x43 /* incomplete. */ + /* If you wish to compile coreboot images with a windows license key + * built in, you need to extract the ACPI SLIC from your machine and + * add it here. + */ +}; + +unsigned long acpi_create_slic(unsigned long current) +{ + memcpy((void *) current, slic, sizeof(slic)); + return sizeof(slic); +} diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c new file mode 100644 index 0000000000..d726678df5 --- /dev/null +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -0,0 +1,370 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "dmi.h" + +extern unsigned char AmlCode[]; + +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable COM port(s) */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x00; + + /* IGD Displays */ + gnvs->ndid = 2; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000410; + gnvs->did[2] = 0x80000320; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +static long acpi_create_ecdt(acpi_ecdt_t * ecdt) +{ + /* Attention: Make sure these match the values from + * the DSDT's ec.asl + */ + static const char ec_id[] = "\\_SB.PCI0.LPCB.EC0"; + int ecdt_len = sizeof(acpi_ecdt_t) + strlen(ec_id) + 1; + + acpi_header_t *header = &(ecdt->header); + + memset((void *) ecdt, 0, ecdt_len); + + /* fill out header fields */ + memcpy(header->signature, "ECDT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = ecdt_len; + header->revision = 1; + + /* Location of the two EC registers */ + ecdt->ec_control.space_id = ACPI_ADDRESS_SPACE_IO; + ecdt->ec_control.bit_width = 8; + ecdt->ec_control.bit_offset = 0; + ecdt->ec_control.addrl = 0x66; + ecdt->ec_control.addrh = 0; + + ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ + ecdt->ec_data.bit_width = 8; + ecdt->ec_data.bit_offset = 0; + ecdt->ec_data.addrl = 0x62; + ecdt->ec_data.addrh = 0; + + ecdt->uid = 1; // Must match _UID of the EC0 node. + + ecdt->gpe_bit = 23; // SCI interrupt within GPEx_STS + + strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id)); + + header->checksum = + acpi_checksum((void *) ecdt, ecdt_len); + + return header->length; +} + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, 0x0005, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, 0x0005, 0x01); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + acpi_header_t *ecdt; + + void *gnvs, *smi1; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x00000518 coreboot table forwarder + * 0x00000600 - 0x00000??? realmode trampoline + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEDEAD) { + printk(BIOS_DEBUG, "ACPI: Patching up SMI1 area in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x100 bytes + break; + } + } + + /* Keep pointer around */ + smi1 = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, smi1); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * ECDT\n"); + ecdt = (acpi_header_t *)current; + current += acpi_create_ecdt((acpi_ecdt_t *)current); + ALIGN_CURRENT; + acpi_add_table(rsdp, ecdt); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); + memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); +#if CONFIG_WRITE_HIGH_TABLES == 1 + memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); + current += DMI_TABLE_SIZE; + ALIGN_CURRENT; +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/getac/p470/chip.h b/src/mainboard/getac/p470/chip.h new file mode 100644 index 0000000000..17c6f00905 --- /dev/null +++ b/src/mainboard/getac/p470/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config { + int nothing; +}; diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout new file mode 100644 index 0000000000..73ea031043 --- /dev/null +++ b/src/mainboard/getac/p470/cmos.layout @@ -0,0 +1,145 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +#936 48 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb new file mode 100644 index 0000000000..26939772ad --- /dev/null +++ b/src/mainboard/getac/p470/devicetree.cb @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i945 + + device lapic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + # autodetect: + #device pci 01.0 off end # i945 PCIe root port + #device pci 02.0 on end # vga controller + #device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0a" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x0a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x0a" + register "pirqh_routing" = "0x0a" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi8_routing" = "1" # EXTSMI low active + register "gpi7_routing" = "2" # ECSCI low active + + # GPE0 Enables + register "gpe0_en" = "0x00800106" + register "alt_gp_smi_en" = "0x0100" + + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 on end # PCIe port 2 + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + chip southbridge/ti/pcixx12 + + end + end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/smsc/fdc37n972 + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # ACPI PM + end + # 2e.2 does not exist + device pnp 2e.3 off # Parallel port + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off + end + #device pnp 2e.6 on # RTC + # io 0x60 = 0x70 + # io 0x62 = 0x74 + #end + device pnp 2e.7 off # Keyboard + end + device pnp 2e.8 off # EC + io 0x60 = 0x62 + end + #device pnp 2e.9 on # Mailbox + #end + end + chip superio/smsc/sio10n268 + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + #device pnp 4e.2 on # COM3 + # io 0x60 = 0x3e8 + # irq 0x70 = 11 + #end + #device pnp 4e.3 on # COM4 + # io 0x60 = 0x2e8 + # irq 0x70 = 10 + #end + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 4e.7 off # GPIO1, GAME, MIDI + end + device pnp 4e.8 off # GPIO2 + end + device pnp 4e.9 off # GPIO3/4 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b off # HWM + end + end + + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end +end diff --git a/src/mainboard/getac/p470/dmi.h b/src/mainboard/getac/p470/dmi.h new file mode 100644 index 0000000000..fde4d8a6f7 --- /dev/null +++ b/src/mainboard/getac/p470/dmi.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define DMI_TABLE_SIZE 0x55 + +static const u8 dmi_table[DMI_TABLE_SIZE] = { + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, + 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, + 0x30, 0x30, 0x38, 0x00, 0x00 +}; diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl new file mode 100644 index 0000000000..f6c6cf785d --- /dev/null +++ b/src/mainboard/getac/p470/dsdt.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define ENABLE_TPM +#undef ENABLE_FDC // There is no Floppy for this laptop + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + #include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include "../../../northbridge/intel/i945/acpi/i945.asl" + #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + } + } + + /* Chipset specific sleep states */ + #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" +} diff --git a/src/mainboard/getac/p470/ec.c b/src/mainboard/getac/p470/ec.c new file mode 100644 index 0000000000..2fe44afb8a --- /dev/null +++ b/src/mainboard/getac/p470/ec.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <delay.h> +#include "ec.h" + +int send_ec_command(u8 command) +{ + int timeout; + + timeout = 0x7ff; + while ((inb(EC_SC) & EC_IBF) && --timeout) { + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + command); + // return -1; + } + + outb(command, EC_SC); + return 0; +} + +int send_ec_data(u8 data) +{ + int timeout; + + timeout = 0x7ff; + while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0 + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n", + data); + // return -1; + } + + outb(data, EC_DATA); + + return 0; +} + +int send_ec_data_nowait(u8 data) +{ + outb(data, EC_DATA); + + return 0; +} + +u8 recv_ec_data(void) +{ + int timeout; + u8 data; + + timeout = 0x7fff; + while (--timeout) { // Wait for OBF = 1 + if (inb(EC_SC) & EC_OBF) { + break; + } + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n"); + // return -1; + } + + data = inb(EC_DATA); + printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data); + + return data; +} + +u8 ec_read(u8 addr) +{ + send_ec_command(0x80); + send_ec_data(addr); + + return recv_ec_data(); +} + +int ec_write(u8 addr, u8 data) +{ + send_ec_command(0x81); + send_ec_data(addr); + return send_ec_data(data); +} + +int ec_dump_status(void) +{ + u8 ec_sc = inb(EC_SC); + printk(BIOS_DEBUG, "Embedded Controller Status: "); + if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT "); + if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT "); + if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST "); + if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD "); + if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF "); + if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF "); + printk(BIOS_DEBUG, "\n"); + + return ec_sc; +} + + +/* ********************************** */ + +int send_ec_oem_command(u8 command) +{ + int timeout; + + timeout = 0x7ff; + while ((inb(EC_OEM_SC) & EC_IBF) && --timeout) { + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n", + command); + // return -1; + } + + outb(command, EC_OEM_SC); + return 0; +} + +int send_ec_oem_data(u8 data) +{ + int timeout; + + timeout = 0x7ff; + while ((inb(EC_OEM_SC) & EC_IBF) && --timeout) { // wait for IBF = 0 + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", + data); + // return -1; + } + + outb(data, EC_OEM_DATA); + + return 0; +} + +int send_ec_oem_data_nowait(u8 data) +{ + outb(data, EC_OEM_DATA); + + return 0; +} + +u8 recv_ec_oem_data(void) +{ + int timeout; + u8 data; + + timeout = 0x7fff; + while (--timeout) { // Wait for OBF = 1 + if (inb(EC_OEM_SC) & EC_OBF) { + break; + } + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "\nTimeout while receiving OEM data from EC!\n"); + // return -1; + } + + data = inb(EC_OEM_DATA); + // printk(BIOS_SPEW, "recv_ec_oem_data: 0x%02x\n", data); + + return data; +} + +u8 ec_oem_read(u8 addr) +{ + send_ec_oem_command(0x80); + send_ec_oem_data(addr); + + return recv_ec_oem_data(); +} + +int ec_oem_write(u8 addr, u8 data) +{ + send_ec_oem_command(0x81); + send_ec_oem_data(addr); + return send_ec_oem_data(data); +} + +int ec_oem_dump_status(void) +{ + u8 ec_sc = inb(EC_OEM_SC); + printk(BIOS_DEBUG, "Embedded Controller Status: "); + if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT "); + if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT "); + if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST "); + if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD "); + if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF "); + if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF "); + printk(BIOS_DEBUG, "\n"); + + return ec_sc; +} + diff --git a/src/mainboard/getac/p470/ec.h b/src/mainboard/getac/p470/ec.h new file mode 100644 index 0000000000..1fe21e5eb5 --- /dev/null +++ b/src/mainboard/getac/p470/ec.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MAINBOARD_EC_H +#define _MAINBOARD_EC_H + +#define EC_DATA 0x62 +#define EC_SC 0x66 + + +#define EC_OEM_DATA 0x68 +#define EC_OEM_SC 0x6c + +/* EC_SC input */ +#define EC_SMI_EVT (1 << 6) // 1: SMI event pending +#define EC_SCI_EVT (1 << 5) // 1: SCI event pending +#define EC_BURST (1 << 4) // controller is in burst mode +#define EC_CMD (1 << 3) // 1: byte in data register is command + // 0: byte in data register is data +#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) +/* EC_SC output */ +#define RD_EC 0x80 // Read Embedded Controller +#define WR_EC 0x81 // Write Embedded Controller +#define BE_EC 0x82 // Burst Enable Embedded Controller +#define BD_EC 0x83 // Burst Disable Embedded Controller +#define QR_EC 0x84 // Query Embedded Controller + +int send_ec_command(u8 command); +int send_ec_data(u8 data); +int send_ec_data_nowait(u8 data); +u8 recv_ec_data(void); +u8 ec_read(u8 addr); +int ec_write(u8 addr, u8 data); + +int send_ec_oem_command(u8 command); +int send_ec_oem_data(u8 data); +int send_ec_oem_data_nowait(u8 data); +u8 recv_ec_oem_data(void); +u8 ec_oem_read(u8 addr); +int ec_oem_write(u8 addr, u8 data); + +int ec_dump_status(void); +int ec_oem_dump_status(void); +#endif + diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c new file mode 100644 index 0000000000..dcce4674a2 --- /dev/null +++ b/src/mainboard/getac/p470/fadt.c @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; // S4 command disabled + fadt->pstate_cnt = PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/getac/p470/hda_verb.h b/src/mainboard/getac/p470/hda_verb.h new file mode 100644 index 0000000000..ab9c55772c --- /dev/null +++ b/src/mainboard/getac/p470/hda_verb.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor ID / Device ID + 0x10714700, // Subsystem ID + 0x0000000d, // Number of jacks + + /* HDA Codec Subsystem ID Verb Table: 0x10ec0000 */ + 0x00172000, + 0x00172100, + 0x001722EC, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + /* Pin Complex (NID 0x14) */ + 0x01471C10, + 0x01471D01, + 0x01471E13, + 0x01471F99, + /* Pin Complex (NID 0x15) */ + 0x01571C20, + 0x01571D40, + 0x01571E21, + 0x01571F01, + /* Pin Complex (NID 0x16) */ + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + /* Pin Complex (NID 0x18) */ + 0x01871C30, + 0x01871D98, + 0x01871EA1, + 0x01871F01, + /* Pin Complex (NID 0x19) */ + 0x01971C31, + 0x01971D09, + 0x01971EA3, + 0x01971F99, + /* Pin Complex (NID 0x1A) */ + 0x01A71C3F, + 0x01A71D98, + 0x01A71EA1, + 0x01A71F02, + /* Pin Complex (NID 0x1B) */ + 0x01B71C1F, + 0x01B71D40, + 0x01B71E21, + 0x01B71F02, + /* Pin Complex (NID 0x1C) */ + 0x01C71CF0, + 0x01C71D11, + 0x01C71E11, + 0x01C71F41, + /* Pin Complex (NID 0x1D) */ + 0x01D71CF0, + 0x01D71D11, + 0x01D71E11, + 0x01D71F41, + /* Pin Complex (NID 0x1E) */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin Complex (NID 0x1F) */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, +}; + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c new file mode 100644 index 0000000000..919bafc8e6 --- /dev/null +++ b/src/mainboard/getac/p470/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c new file mode 100644 index 0000000000..c2e9e1831e --- /dev/null +++ b/src/mainboard/getac/p470/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include "chip.h" +#include "hda_verb.h" + +#include "ec.c" + +#define MAX_LCD_BRIGHTNESS 0xd8 + +static void ec_enable(void) +{ + u16 keymap; + /* Enable Hotkey SCI */ + + /* Fn key map; F1 = [0] ... F12 = [11] */ + keymap = 0x5f1; + send_ec_oem_command(0x45); + send_ec_oem_data(0x09); // SCI + // send_ec_oem_data(0x08); // SMI# + send_ec_oem_data(keymap >> 8); + send_ec_oem_data(keymap & 0xff); + + /* Enable Backlight */ + ec_write(0x17, MAX_LCD_BRIGHTNESS); + + /* Notify EC system is in ACPI mode */ + send_ec_oem_command(0x5e); + send_ec_oem_data(0xea); + send_ec_oem_data(0x0c); + send_ec_oem_data(0x01); +} + +static void pcie_limit_power(void) +{ +#if 0 + // This piece of code needs further debugging as it crashes the + // machine. It should set the slot numbers and enable power + // limitation for the PCIe slots. + + device_t dev; + + dev = dev_find_slot(0, PCI_DEVFN(28,0)); + if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); + + dev = dev_find_slot(0, PCI_DEVFN(28,1)); + if (dev) pci_write_config32(dev, 0x54, 0x0018a0e0); + + dev = dev_find_slot(0, PCI_DEVFN(28,2)); + if (dev) pci_write_config32(dev, 0x54, 0x0020a0e0); + + dev = dev_find_slot(0, PCI_DEVFN(28,3)); + if (dev) pci_write_config32(dev, 0x54, 0x0028a0e0); +#endif +} + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} + +static void mainboard_init(device_t dev) +{ + ec_enable(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). Is there no mainboard_init()? +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + pcie_limit_power(); + verb_setup(); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("Getac P470 Rugged Notebook") + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c new file mode 100644 index 0000000000..c7fe3f74f1 --- /dev/null +++ b/src/mainboard/getac/p470/mainboard_smi.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "southbridge/intel/i82801gx/i82801gx_nvs.h" +#include "northbridge/intel/i945/udelay.c" +#include "ec.c" + +#define MAX_LCD_BRIGHTNESS 0xd8 + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + u8 reg8; + u32 reg32; + + switch (smif) { + case 0x2b: + printk(BIOS_DEBUG, "CPU power state switch\n"); + // TODO, move to CPU handler? + break; + case 0x3d: + printk(BIOS_DEBUG, "Enable C-State SMM coordination\n"); + // TODO, move to CPU handler? + break; + case 0x46: + printk(BIOS_DEBUG, "S3 DTS SMI (completely re-enable DTS)\n"); + // TODO, move to CPU handler? + break; + case 0x47: + printk(BIOS_DEBUG, "S4 DTS SMI (Update NVS DTS temperature)\n"); + // TODO, move to CPU handler? + break; + case 0xc0: + printk(BIOS_DEBUG, "Disable RF\n"); + // TODO + break; + case 0xd0: + printk(BIOS_DEBUG, "ACBS LAN Power on\n"); + // TODO + break; + case 0xd1: + printk(BIOS_DEBUG, "ACBS LAN Power off\n"); + // TODO + break; + case 0xd2: + printk(BIOS_DEBUG, "Check AC status\n"); + // TODO + break; + case 0xd3: + printk(BIOS_DEBUG, "Enable Bluetooth\n"); + // TODO + break; + case 0xd4: + printk(BIOS_DEBUG, "Disable Bluetooth\n"); + // TODO + break; + case 0xd5: + printk(BIOS_DEBUG, "Set Brightness\n"); + reg8 = gnvs->brtl; + printk(BIOS_DEBUG, "brtl: %x\n", reg8); + ec_write(0x17, reg8); + break; + case 0xd6: + printk(BIOS_DEBUG, "Get Brightness\n"); + reg8 = ec_read(0x17); + printk(BIOS_DEBUG, "brtl: %x\n", reg8); + gnvs->brtl = reg8; + break; + case 0xd7: + printk(BIOS_DEBUG, "Get ECO mode status\n"); + // TODO + break; + case 0xd8: + printk(BIOS_DEBUG, "Get sunlight readable status\n"); + // TODO + break; + case 0xd9: + printk(BIOS_DEBUG, "Get docking connection\n"); + // TODO + break; + case 0xda: + printk(BIOS_DEBUG, "Power off docking\n"); + // TODO + break; + case 0xdc: + printk(BIOS_DEBUG, "EC: Turn on LED on ECO enable\n"); + // TODO + break; + case 0xdd: + printk(BIOS_DEBUG, "EC: Turn off LED on ECO disable\n"); + // TODO + break; + case 0xde: + printk(BIOS_DEBUG, "LAN power off\n"); + reg32 = inl(DEFAULT_GPIOBASE + GP_LVL); + reg32 |= (1 << 24); // Disable LAN Power + outl(reg32, DEFAULT_GPIOBASE + GP_LVL); + break; + case 0xdf: + printk(BIOS_DEBUG, "RF enable\n"); + // TODO + break; + case 0xe0: + printk(BIOS_DEBUG, "Get RTC wake flag\n"); + // TODO + break; + case 0xe1: + printk(BIOS_DEBUG, "Hotkey function\n"); + // TODO + break; + case 0xe3: + printk(BIOS_DEBUG, "ECO disable\n"); + // TODO + break; + default: + return 0; + } + + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ + gnvs->smif = 0; + return 1; +} + +static void mainboard_smi_hotkey(u8 hotkey) +{ + u8 reg8; + + switch (hotkey) { + case 0x3b: break; // Fn+F1 + case 0x3c: break; // Fn+F2 + case 0x3d: break; // Fn+F3 + case 0x3e: break; // Fn+F4 + case 0x3f: break; // Fn+F5 + case 0x40: // Fn+F6 (Decrease Display Brightness) + reg8 = ec_read(0x17); + reg8 = (reg8 > 8) ? (reg8 - 8) : 0; + ec_write(0x17, reg8); + return; + case 0x41: // Fn+F7 (Increase Display Brightness) + reg8 = ec_read(0x17); + reg8 += 8; + reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; + ec_write(0x17, reg8); + return; + case 0x42: break; // Fn+F8 + case 0x43: break; // Fn+F9 + case 0x44: break; // Fn+F10 + case 0x57: break; // Fn+F11 + case 0x58: break; // Fn+F12 + } + printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey); +} + +void mainboard_smi_gpi(u16 gpi_sts) +{ + u8 source, hotkey; + send_ec_oem_command(0x5c); + source = recv_ec_oem_data(); + + switch (source) { + case 0: + // Some kind of ACK? + break; + case 1: + send_ec_oem_command(0x59); + hotkey = recv_ec_oem_data(); + mainboard_smi_hotkey(hotkey); + break; + default: + printk(BIOS_DEBUG, "EC SMI source: %02x\n", source); + } +} + diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c new file mode 100644 index 0000000000..429c1796dd --- /dev/null +++ b/src/mainboard/getac/p470/mptable.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "P470 "; + struct mp_config_table *mc; + int i; + int max_pci_bus, isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + max_pci_bus = 5; // XXX read me from bridges. + + /* ISA bus follows */ + isa_bus = max_pci_bus + 1; + + /* Bus: Bus ID Type */ + for (i=0; i <= max_pci_bus; i++) + smp_write_bus(mc, i, "PCI "); + + smp_write_bus(mc, isa_bus, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + + /* Legacy Interrupts */ + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf); + + /* Builtin devices on Bus 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + + /* Firewire 4:0.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + + // riser slot top 5:8.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + // riser slot middle 5:9.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + // riser slot bottom 5:a.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + + /* Onboard Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c new file mode 100644 index 0000000000..ecc9e4bb03 --- /dev/null +++ b/src/mainboard/getac/p470/romstage.c @@ -0,0 +1,423 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Configuration of the i945 driver */ +#define CHIPSET_I945GM 1 +#define CHANNEL_XOR_RANDOMIZATION 1 + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> + +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#include <console/console.h> +#include <cpu/x86/bist.h> + +#if CONFIG_USBDEBUG_DIRECT +#define DBGP_DEFAULT 0 +#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" +#include "pc80/usbdebug_direct_serial.c" +#endif + +#include "lib/ramtest.c" +#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" + +#include "northbridge/intel/i945/udelay.c" + +#include "southbridge/intel/i82801gx/i82801gx.h" +static void setup_ich7_gpios(void) +{ + u32 gpios; + + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f28f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e809c3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + // Power On value is eede1fbf, we set: (TODO explain why) + // -- [21] = 1 + // -- [20] = 0 + // -- [18] = 0 + // -- [17] = 0 + // -- [13] = 1 + // -- [05] = 0 + // -- [04] = 0 + // -- [03] = 0 + // -- [02] = 0 + // We should probably do this explicitly bitwise, see below. + outl(0xeee83f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00000180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000e6, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000d0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00000034, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + + printk(BIOS_SPEW, "\n Initializing drive bay...\n"); + gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 + gpios |= (1 << 0); // GPIO33 = ODD + gpios |= (1 << 1); // GPIO34 = IDE_RST# + outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + + gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level + gpios &= ~(1 << 13); // ?? + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + + printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); + gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level + gpios &= ~(1 << 24); // Enable LAN Power + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ +} + +#include "northbridge/intel/i945/early_init.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i945/raminit.h" +#include "northbridge/intel/i945/raminit.c" +#include "northbridge/intel/i945/errata.c" +#include "northbridge/intel/i945/debug.c" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + // Enable 0x02e0 - 0x2ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); + // Enable 0x600 - 0x6ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // Enable 0x68 - 0x6f + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); +} + + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +static void pnp_write_register(device_t dev, int reg, int val) +{ + unsigned int port = dev >> 8; + outb(reg, port); + outb(val, port+1); +} + +static void early_superio_config(void) +{ + device_t dev; + + dev=PNP_DEV(0x4e, 0x00); + + pnp_enter_ext_func_mode(dev); + pnp_write_register(dev, 0x02, 0x0e); // UART power + pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ + pnp_write_register(dev, 0x1e, 1); // no 32khz clock + pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_register(dev, 0x2c, 0); // DMA0 FIR + pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + + pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR + pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR + pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR + pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR + pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL + + pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT + pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT + pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT + pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR + pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL + pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1 + pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2 + pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3 + + pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5 + pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6 + pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7 + pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8 + pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9 + pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10 + + pnp_exit_ext_func_mode(dev); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042220; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0232; + RCBA16(0x3142) = 0x3246; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x3216; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; + + + /* This should probably go into the ACPI enable trap */ + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA32(0x1e84) = 0x00020001; + RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +#include <cbmem.h> + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM_ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + + if (bist == 0) { + enable_lapic(); + } + +#if 0 + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + udelay(200); +#endif + + ich7_enable_lpc(); + early_superio_config(); + + /* Set up the console */ + uart_init(); + +#if CONFIG_USBDEBUG_DIRECT + i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); + early_usbdebug_direct_init(); +#endif + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(boot_mode); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if CONFIG_HAVE_ACPI_RESUME == 0 + /* When doing resume, we must not overwrite RAM */ +#if defined(DEBUG_RAM_SETUP) + sdram_dump_mchbar_registers(); + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif +#endif + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } +#endif +} + diff --git a/src/mainboard/getac/p470/rtl8168.c b/src/mainboard/getac/p470/rtl8168.c new file mode 100644 index 0000000000..f0f98d20f4 --- /dev/null +++ b/src/mainboard/getac/p470/rtl8168.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <delay.h> + +// #define RTL8168_DEBUG 1 + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. + +#ifdef RTL8168_DEBUG + u8 reg8; + + printk(BIOS_DEBUG, "Resetting device... "); + pci_write_config8(dev, 0x37, (1 << 4)); + do { + reg8 = pci_read_config8(dev, 0x37); + reg8 &= (1 << 4); + } while (reg8); + printk(BIOS_DEBUG, "ok\n"); + + printk(BIOS_DEBUG, "Eeprom Auto-Load... "); + reg8 = pci_read_config8(dev, 0x50); + reg8 &= 0x3f; + reg8 |= (1 << 6); + pci_write_config8(dev, 0x50, reg8); + mdelay(3); + printk(BIOS_DEBUG, "ok\n"); +#endif +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8168_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x10ec, + .device = 0x8168, +}; + +#ifdef RTL8168_DEBUG +static const struct pci_driver rtl8129_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x10ec, + .device = 0x8129, +}; +#endif + |