summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/Kconfig6
-rw-r--r--src/mainboard/google/hatch/Makefile.inc1
-rw-r--r--src/mainboard/google/hatch/romstage_spd_smbus.c50
3 files changed, 56 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 219be2265a..e339693fcb 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -60,7 +60,11 @@ config DIMM_SPD_SIZE
config ROMSTAGE_SPD_CBFS
bool
- default y
+ default y if !ROMSTAGE_SPD_SMBUS
+
+config ROMSTAGE_SPD_SMBUS
+ bool
+ default n
config DRIVER_TPM_SPI_BUS
default 0x1
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc
index a226bd623c..7ad7849b58 100644
--- a/src/mainboard/google/hatch/Makefile.inc
+++ b/src/mainboard/google/hatch/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
+romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c
new file mode 100644
index 0000000000..74d59a59f5
--- /dev/null
+++ b/src/mainboard/google/hatch/romstage_spd_smbus.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ struct cnl_mb_cfg memcfg;
+ variant_memory_params(&memcfg);
+
+ /* Read spd block to get memory config */
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52, },
+ };
+
+ /* Access memory info through SMBUS. */
+ get_spd_smbus(&blk);
+ memcfg.spd[0].read_type = READ_SPD_MEMPTR;
+ memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
+ memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0];
+
+ memcfg.spd[1].read_type = NOT_EXISTING;
+
+ memcfg.spd[2].read_type = READ_SPD_MEMPTR;
+ memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
+ memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1];
+
+ memcfg.spd[3].read_type = NOT_EXISTING;
+ dump_spd_info(&blk);
+
+ /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */
+ memcfg.vref_ca_config = 2;
+
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}