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-rw-r--r--src/mainboard/emulation/qemu-q35/bootblock.c4
-rw-r--r--src/mainboard/intel/harcuvar/romstage.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index fafa03b45d..efb3a4f7e1 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -16,12 +16,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c
index fbad79836f..0373c01c60 100644
--- a/src/mainboard/intel/harcuvar/romstage.c
+++ b/src/mainboard/intel/harcuvar/romstage.c
@@ -12,7 +12,7 @@
/*
* Define platform specific Memory Down Configure structure.
*
- * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG
+ * If CONFIG(ENABLE_FSP_MEMORY_DOWN) is enabled, the MEMORY_DOWN_CONFIG
* structure should be customized to match the design.
*
* .SlotState indicates the memory down state of the specific channel/DIMM.