diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 1d7812b3e0..6f9b9d1392 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -64,10 +64,6 @@ void main(void) uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif - /* used for MMU and CBMEM setup, in MB */ - u32 dram_start_mb = (uintptr_t)_dram/MiB; - u32 dram_size_mb = CONFIG_DRAM_SIZE_MB; - u32 dram_end_mb = dram_start_mb + dram_size_mb; console_init(); @@ -80,18 +76,12 @@ void main(void) #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif - mmu_init(); - /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start_mb, DCACHE_OFF); - /* DRAM is cached. */ - mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); - /* A window for DMA is uncached. */ + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); - /* The space above DRAM is uncached. */ - if (dram_end_mb < 4096) - mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); - dcache_mmu_enable(); cbmem_initialize_empty(); |