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-rw-r--r--src/mainboard/amd/rumba/Kconfig3
-rw-r--r--src/mainboard/amd/rumba/romstage.c22
-rw-r--r--src/mainboard/lippert/frontrunner/Kconfig3
-rw-r--r--src/mainboard/lippert/frontrunner/romstage.c32
-rw-r--r--src/mainboard/olpc/btest/Kconfig3
-rw-r--r--src/mainboard/olpc/btest/romstage.c17
-rw-r--r--src/mainboard/olpc/rev_a/Kconfig3
-rw-r--r--src/mainboard/olpc/rev_a/romstage.c17
-rw-r--r--src/mainboard/wyse/s50/Kconfig3
-rw-r--r--src/mainboard/wyse/s50/romstage.c31
10 files changed, 37 insertions, 97 deletions
diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig
index 98bea7e33c..3a76969a55 100644
--- a/src/mainboard/amd/rumba/Kconfig
+++ b/src/mainboard/amd/rumba/Kconfig
@@ -23,8 +23,9 @@ config BOARD_AMD_RUMBA
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index ca2aac9cd5..120720f77a 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -2,7 +2,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
@@ -99,22 +98,9 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- /* total physical memory */
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- /* traditional memory 0kB-512kB, 512kB-1MB */
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
+#include "cpu/amd/model_lx/msrinit.c"
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-
- /* put code in northbridge[init].c here */
-}
-
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -122,13 +108,15 @@ static void main(unsigned long bist)
SystemPreInit();
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
cs5536_early_setup();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig
index f99058b8cb..fdf507d6a6 100644
--- a/src/mainboard/lippert/frontrunner/Kconfig
+++ b/src/mainboard/lippert/frontrunner/Kconfig
@@ -4,8 +4,9 @@ config BOARD_LIPPERT_FRONTRUNNER
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index f6ef0bba76..c074fccdad 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -2,7 +2,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
@@ -10,6 +9,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
+#include "southbridge/amd/cs5535/cs5535.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -46,31 +46,9 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
- __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
- __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
- __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
- __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
- __builtin_wrmsr(0x10000080, 0x3, 0x0);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
- __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
- __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
- __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
- __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
- __builtin_wrmsr(0x50002001, 0x27, 0x0);
- __builtin_wrmsr(0x4c002001, 0x1, 0x0);
-}
+#include "cpu/amd/model_lx/msrinit.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -85,6 +63,10 @@ static void main(unsigned long bist)
cs5535_early_setup();
print_err("done cs5535 early\n");
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
print_err("done pll_reset\n");
diff --git a/src/mainboard/olpc/btest/Kconfig b/src/mainboard/olpc/btest/Kconfig
index 9ed3a33a36..3b95a8ba50 100644
--- a/src/mainboard/olpc/btest/Kconfig
+++ b/src/mainboard/olpc/btest/Kconfig
@@ -4,8 +4,9 @@ config BOARD_OLPC_BTEST
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c
index a0e71d8584..a6d675fadd 100644
--- a/src/mainboard/olpc/btest/romstage.c
+++ b/src/mainboard/olpc/btest/romstage.c
@@ -2,7 +2,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
@@ -132,16 +131,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void gpio_init(void)
{
@@ -155,7 +145,7 @@ static void gpio_init(void)
outl(m, GPIOL_EVENTS_ENABLE);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -175,6 +165,9 @@ static void main(unsigned long bist)
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
diff --git a/src/mainboard/olpc/rev_a/Kconfig b/src/mainboard/olpc/rev_a/Kconfig
index fd8a712564..6c097c1135 100644
--- a/src/mainboard/olpc/rev_a/Kconfig
+++ b/src/mainboard/olpc/rev_a/Kconfig
@@ -4,8 +4,9 @@ config BOARD_OLPC_REV_A
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c
index a0e71d8584..a6d675fadd 100644
--- a/src/mainboard/olpc/rev_a/romstage.c
+++ b/src/mainboard/olpc/rev_a/romstage.c
@@ -2,7 +2,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
@@ -132,16 +131,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void gpio_init(void)
{
@@ -155,7 +145,7 @@ static void gpio_init(void)
outl(m, GPIOL_EVENTS_ENABLE);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -175,6 +165,9 @@ static void main(unsigned long bist)
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig
index eb1d1e5cc5..21d3eccf4b 100644
--- a/src/mainboard/wyse/s50/Kconfig
+++ b/src/mainboard/wyse/s50/Kconfig
@@ -23,8 +23,9 @@ config BOARD_WYSE_S50
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 8a6e1213c9..b2d62a2bb1 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -23,7 +23,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
@@ -122,32 +121,9 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
-static void msr_init(void)
-{
- /* Setup access to cache under 1MB.
- __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
-
- __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */
- __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */
- __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */
- __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */
- __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */
- __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */
- __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */
- __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */
-
- /* put code in northbridge[init].c here */
-}
-
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -166,6 +142,9 @@ static void main(unsigned long bist)
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 13:25:16 +0000