diff options
Diffstat (limited to 'src/northbridge/amd/agesa/family14/state_machine.c')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/state_machine.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index df55efa749..91a8f70259 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -29,24 +29,30 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { + if (!boot_cpu()) + return; + + if (!CONFIG(ROMCC_BOOTBLOCK)) + sb_Poweron_Init(); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured * and C6DramLock bit has been set. * * As a workaround, do a hard reset to clear C6DramLock bit. */ + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x18, 2); #else struct device *dev = pcidev_on_root(0x18, 2); #endif - if (boot_cpu()) { - u32 mct_cfg_lo = pci_read_config32(dev, 0x118); - if (mct_cfg_lo & (1<<19)) { - printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); - system_reset(); - } + u32 mct_cfg_lo = pci_read_config32(dev, 0x118); + if (mct_cfg_lo & (1<<19)) { + printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); + system_reset(); } + } void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |