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-rw-r--r--src/northbridge/amd/amdfam10/acpi.c34
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10_util.asl2
-rw-r--r--src/northbridge/amd/amdfam10/debug.c52
-rw-r--r--src/northbridge/amd/amdfam10/early_ht.c12
-rw-r--r--src/northbridge/amd/amdfam10/get_pci1234.c18
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c96
-rw-r--r--src/northbridge/amd/amdfam10/raminit_amdmct.c2
-rw-r--r--src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c10
-rw-r--r--src/northbridge/amd/amdfam10/reset_test.c4
-rw-r--r--src/northbridge/amd/amdfam10/setup_resource_map.c12
10 files changed, 121 insertions, 121 deletions
diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index d4ad9a409d..51da7d6c88 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -31,7 +31,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 l
device_t cpu;
int cpu_index = 0;
- for(cpu = all_devices; cpu; cpu = cpu->next) {
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;
@@ -50,7 +50,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current)
device_t cpu;
int cpu_index = 0;
- for(cpu = all_devices; cpu; cpu = cpu->next) {
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;
@@ -94,9 +94,9 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
* next range is from 1M---
* So will cut off before 1M in the mem range
*/
- if((basek+sizek)<1024) return;
+ if ((basek+sizek)<1024) return;
- if(basek<1024) {
+ if (basek<1024) {
sizek -= 1024 - basek;
basek = 1024;
}
@@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current)
*p = (u8) nodes;
p += 8;
- for(i=0;i<nodes;i++) {
- for(j=0;j<nodes; j++) {
- if(i==j)
+ for (i=0;i<nodes;i++) {
+ for (j=0;j<nodes; j++) {
+ if (i==j)
p[i*nodes+j] = 10;
else
p[i*nodes+j] = 16;
@@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_name("BUSN");
acpigen_write_package(HC_NUMS);
- for(i=0; i<HC_NUMS; i++) {
+ for (i=0; i<HC_NUMS; i++) {
acpigen_write_dword(sysconf.ht_c_conf_bus[i]);
}
// minus the opcode
@@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_NUMS * 4);
- for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
+ for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base
acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask
}
@@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_NUMS * 2);
- for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
+ for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
acpigen_write_dword(sysconf.conf_io_addrx[i]);
acpigen_write_dword(sysconf.conf_io_addr[i]);
}
@@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_POSSIBLE_NUM);
- for(i=0;i<sysconf.hc_possible_num;i++) {
+ for (i=0;i<sysconf.hc_possible_num;i++) {
acpigen_write_dword(sysconf.pci1234[i]);
}
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x00000000);
}
// minus the opcode
@@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_package(HC_POSSIBLE_NUM);
- for(i=0;i<sysconf.hc_possible_num;i++) {
+ for (i=0;i<sysconf.hc_possible_num;i++) {
acpigen_write_dword(sysconf.hcdn[i]);
}
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x20202020);
}
// minus the opcode
@@ -299,10 +299,10 @@ void northbridge_acpi_write_vars(device_t device)
u8 CBST, CBB2, CBS2;
- if(CONFIG_CBB == 0xff) {
+ if (CONFIG_CBB == 0xff) {
CBST = (u8) (0x0f);
} else {
- if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
+ if ((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
CBST = (u8) (0x0f);
} else {
CBST = (u8) (0x00);
@@ -311,7 +311,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_write_name_byte("CBST", CBST);
- if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
+ if ((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
CBS2 = 0x0f;
CBB2 = (u8)(CONFIG_CBB-1);
} else {
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl
index e10efb4623..bf0d177e14 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.asl
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl
@@ -66,7 +66,7 @@ Scope (\_SB)
Method (GHCE, 1, NotSerialized) // check if the HC enabled
{
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
Else { Return (0x00) }
}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 27bd3319fe..f8e535851a 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -35,7 +35,7 @@ static void print_debug_pci_dev(u32 dev)
static inline void print_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
+ for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
u32 id;
@@ -47,10 +47,10 @@ static inline void print_pci_devices(void)
}
print_debug_pci_dev(dev);
printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
- if(((dev>>12) & 0x07) == 0) {
+ if (((dev>>12) & 0x07) == 0) {
u8 hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
- if((hdr_type & 0x80) != 0x80) {
+ if ((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
@@ -60,7 +60,7 @@ static inline void print_pci_devices(void)
static inline void print_pci_devices_on_bus(u32 busn)
{
device_t dev;
- for(dev = PCI_DEV(busn, 0, 0);
+ for (dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
u32 id;
@@ -72,10 +72,10 @@ static inline void print_pci_devices_on_bus(u32 busn)
}
print_debug_pci_dev(dev);
printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
- if(((dev>>12) & 0x07) == 0) {
+ if (((dev>>12) & 0x07) == 0) {
u8 hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
- if((hdr_type & 0x80) != 0x80) {
+ if ((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
@@ -89,13 +89,13 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
int j;
int end = start_reg + size;
- for(i = start_reg; i < end; i+=4) {
+ for (i = start_reg; i < end; i+=4) {
u32 val;
if ((i & 0x0f) == 0) {
printk(BIOS_DEBUG, "\n%04x:",i);
}
val = pci_read_config32(dev, i);
- for(j=0;j<4;j++) {
+ for (j=0;j<4;j++) {
printk(BIOS_DEBUG, " %02x", val & 0xff);
val >>= 8;
}
@@ -116,12 +116,12 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
print_debug_pci_dev(dev);
printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
- for(i = start; i < end; i++) {
+ for (i = start; i < end; i++) {
u32 val;
int j;
printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config32_index_wait(dev, index_reg, i);
- for(j=0;j<4;j++) {
+ for (j=0;j<4;j++) {
printk(BIOS_DEBUG, " %02x", val & 0xff);
val >>= 8;
}
@@ -147,7 +147,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
type<<=28;
- for(i = 0; i < length; i++) {
+ for (i = 0; i < length; i++) {
u32 val;
if ((i & 0x0f) == 0) {
printk(BIOS_DEBUG, "\n%02x:",i);
@@ -161,7 +161,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
static inline void dump_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
+ for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
u32 id;
@@ -173,10 +173,10 @@ static inline void dump_pci_devices(void)
}
dump_pci_device(dev);
- if(((dev>>12) & 0x07) == 0) {
+ if (((dev>>12) & 0x07) == 0) {
u8 hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
- if((hdr_type & 0x80) != 0x80) {
+ if ((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
@@ -186,7 +186,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(u32 busn)
{
device_t dev;
- for(dev = PCI_DEV(busn, 0, 0);
+ for (dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
u32 id;
@@ -198,10 +198,10 @@ static inline void dump_pci_devices_on_bus(u32 busn)
}
dump_pci_device(dev);
- if(((dev>>12) & 0x07) == 0) {
+ if (((dev>>12) & 0x07) == 0) {
u8 hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
- if((hdr_type & 0x80) != 0x80) {
+ if ((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
@@ -214,13 +214,13 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
printk(BIOS_DEBUG, "\n");
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
u32 device;
device = ctrl->spd_addr[i];
if (device) {
int j;
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
- for(j = 0; j < 128; j++) {
+ for (j = 0; j < 128; j++) {
int status;
u8 byte;
if ((j & 0xf) == 0) {
@@ -239,7 +239,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
if (device) {
int j;
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
- for(j = 0; j < 128; j++) {
+ for (j = 0; j < 128; j++) {
int status;
u8 byte;
if ((j & 0xf) == 0) {
@@ -260,11 +260,11 @@ static void dump_smbus_registers(void)
{
u32 device;
printk(BIOS_DEBUG, "\n");
- for(device = 1; device < 0x80; device++) {
+ for (device = 1; device < 0x80; device++) {
int j;
- if( smbus_read_byte(device, 0) < 0 ) continue;
+ if ( smbus_read_byte(device, 0) < 0 ) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
- for(j = 0; j < 256; j++) {
+ for (j = 0; j < 256; j++) {
int status;
u8 byte;
status = smbus_read_byte(device, j);
@@ -287,7 +287,7 @@ static inline void dump_io_resources(u32 port)
int i;
udelay(2000);
printk(BIOS_DEBUG, "%04x:\n", port);
- for(i=0;i<256;i++) {
+ for (i=0;i<256;i++) {
u8 val;
if ((i & 0x0f) == 0) {
printk(BIOS_DEBUG, "%02x:", i);
@@ -305,8 +305,8 @@ static inline void dump_mem(u32 start, u32 end)
{
u32 i;
printk(BIOS_DEBUG, "dump_mem:");
- for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
+ for (i=start;i<end;i++) {
+ if ((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 3e59a324e7..57c992c565 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -79,7 +79,7 @@ static void enumerate_ht_chain(void)
{
pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
}
- while(pos != 0) {
+ while (pos != 0) {
u8 cap;
cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
if (cap == PCI_CAP_ID_HT) {
@@ -96,8 +96,8 @@ static void enumerate_ht_chain(void)
device_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if(next_unitid>=0x18) {
- if(!end_used) {
+ if (next_unitid>=0x18) {
+ if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
@@ -147,18 +147,18 @@ static void enumerate_ht_chain(void)
break;
}
}
- } while((ctrl & (1 << 5)) == 0);
+ } while ((ctrl & (1 << 5)) == 0);
break;
}
}
pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
}
- } while(last_unitid != next_unitid);
+ } while (last_unitid != next_unitid);
out: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
+ if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
u16 flags;
flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index 41c2b33152..a6f679ecad 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -73,29 +73,29 @@ void get_pci1234(void)
//2. so at the same time we need update hsdn with hcdn_reg here
// printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
- for(j=0;j<sysconf.ht_c_num;j++) {
+ for (j=0;j<sysconf.ht_c_num;j++) {
u32 dwordx;
dwordx = sysconf.ht_c_conf_bus[j];
// printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
- if((dwordx & 0x7fd) == dword) { //SBLINK
+ if ((dwordx & 0x7fd) == dword) { //SBLINK
sysconf.pci1234[0] = dwordx;
sysconf.hcdn[0] = sysconf.hcdn_reg[j];
continue;
}
- if((dwordx & 1)) {
+ if ((dwordx & 1)) {
// We need to find out the number of HC
// for exact match
- for(i=1;i<sysconf.hc_possible_num;i++) {
- if((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn
+ for (i=1;i<sysconf.hc_possible_num;i++) {
+ if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
// for 0xffc match or same node
- for(i=1;i<sysconf.hc_possible_num;i++) {
- if((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) {
+ for (i=1;i<sysconf.hc_possible_num;i++) {
+ if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
@@ -104,8 +104,8 @@ void get_pci1234(void)
}
}
- for(i=1;i<sysconf.hc_possible_num;i++) {
- if(!(sysconf.pci1234[i] & 1)) {
+ for (i=1;i<sysconf.hc_possible_num;i++) {
+ if (!(sysconf.pci1234[i] & 1)) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
}
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 19acab61db..42647b1e3a 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -70,7 +70,7 @@ static unsigned fx_devs=0;
device_t get_node_pci(u32 nodeid, u32 fn)
{
#if NODE_NUMS + CONFIG_CDB >= 32
- if((CONFIG_CDB + nodeid) < 32) {
+ if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
@@ -99,7 +99,7 @@ static inline uint8_t is_fam15h(void)
static void get_fx_devs(void)
{
int i;
- for(i = 0; i < FX_DEVS; i++) {
+ for (i = 0; i < FX_DEVS; i++) {
__f0_dev[i] = get_node_pci(i, 0);
__f1_dev[i] = get_node_pci(i, 1);
__f2_dev[i] = get_node_pci(i, 2);
@@ -124,7 +124,7 @@ static void f1_write_config32(unsigned reg, u32 value)
int i;
if (fx_devs == 0)
get_fx_devs();
- for(i = 0; i < fx_devs; i++) {
+ for (i = 0; i < fx_devs; i++) {
device_t dev;
dev = __f1_dev[i];
if (dev && dev->enabled) {
@@ -138,7 +138,7 @@ u32 amdfam10_nodeid(device_t dev)
#if NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
- if(busn != CONFIG_CBB) {
+ if (busn != CONFIG_CBB) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
@@ -395,12 +395,12 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
unsigned nodeid, link = 0;
int result;
res = 0;
- for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
+ for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
device_t dev;
dev = __f0_dev[nodeid];
if (!dev)
continue;
- for(link = 0; !res && (link < 8); link++) {
+ for (link = 0; !res && (link < 8); link++) {
res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
}
}
@@ -422,7 +422,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi
u32 free_reg, reg;
resource = 0;
free_reg = 0;
- for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+ for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
@@ -438,7 +438,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi
}
//Ext conf space
- if(!reg) {
+ if (!reg) {
//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
u32 index = get_io_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
@@ -455,7 +455,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
u32 free_reg, reg;
resource = 0;
free_reg = 0;
- for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
+ for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
@@ -471,7 +471,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
}
//Ext conf space
- if(!reg) {
+ if (!reg) {
//because of Extend conf space, we will never run out of reg,
// but we need one index to differ them. so same node and
// same link can have multi range
@@ -530,7 +530,7 @@ static void amdfam10_read_resources(device_t dev)
u32 nodeid;
struct bus *link;
nodeid = amdfam10_nodeid(dev);
- for(link = dev->link_list; link; link = link->next) {
+ for (link = dev->link_list; link; link = link->next) {
if (link->children) {
amdfam10_link_read_bases(dev, nodeid, link->link_num);
}
@@ -605,7 +605,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if((vga_pri->bus->secondary >= link->secondary ) &&
+ if ((vga_pri->bus->secondary >= link->secondary ) &&
(vga_pri->bus->secondary <= link->subordinate )
)
#endif
@@ -645,11 +645,11 @@ static void amdfam10_set_resources(device_t dev)
amdfam10_create_vga_resource(dev, nodeid);
/* Set each resource we have found */
- for(res = dev->resource_list; res; res = res->next) {
+ for (res = dev->resource_list; res; res = res->next) {
amdfam10_set_resource(dev, res, nodeid);
}
- for(bus = dev->link_list; bus; bus = bus->next) {
+ for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
assign_resources(bus);
}
@@ -711,7 +711,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* Find the already assigned resource pairs */
get_fx_devs();
- for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
+ for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x04);
@@ -719,7 +719,7 @@ static void amdfam10_domain_read_resources(device_t dev)
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
device_t reg_dev;
- if(reg<0xc0) { // mmio
+ if (reg<0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30);
@@ -864,10 +864,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct dram_base_mask_t d;
u32 hole;
d = get_dram_base_mask(i);
- if(!(d.mask & 1)) continue; // no memory on this node
+ if (!(d.mask & 1)) continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0);
- if(hole & 1) { // we find the hole
+ if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
@@ -877,17 +877,17 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
/* We need to double check if there is special set on base reg and limit reg
* are not continuous instead of hole, it will find out its hole_startk.
*/
- if(mem_hole.node_id==-1) {
+ if (mem_hole.node_id==-1) {
resource_t limitk_pri = 0;
- for(i=0; i<sysconf.nodes; i++) {
+ for (i=0; i<sysconf.nodes; i++) {
struct dram_base_mask_t d;
resource_t base_k, limit_k;
d = get_dram_base_mask(i);
- if(!(d.base & 1)) continue;
+ if (!(d.base & 1)) continue;
base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
- if(base_k > 4 *1024 * 1024) break; // don't need to go to check
- if(limitk_pri != base_k) { // we find the hole
+ if (base_k > 4 *1024 * 1024) break; // don't need to go to check
+ if (limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
mem_hole.node_id = i;
break; //only one hole
@@ -927,7 +927,7 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
pci_tolm = 0xffffffffUL;
- for(link = dev->link_list; link; link = link->next) {
+ for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);
}
@@ -960,12 +960,12 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
idx = 0x10;
- for(i = 0; i < sysconf.nodes; i++) {
+ for (i = 0; i < sysconf.nodes; i++) {
struct dram_base_mask_t d;
resource_t basek, limitk, sizek; // 4 1T
d = get_dram_base_mask(i);
- if(!(d.mask & 1)) continue;
+ if (!(d.mask & 1)) continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
sizek = limitk - basek;
@@ -986,7 +986,7 @@ static void amdfam10_domain_set_resources(device_t dev)
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if(pre_sizek>0) {
+ if (pre_sizek>0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -1011,7 +1011,7 @@ static void amdfam10_domain_set_resources(device_t dev)
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#endif
- for(link = dev->link_list; link; link = link->next) {
+ for (link = dev->link_list; link; link = link->next) {
if (link->children) {
assign_resources(link);
}
@@ -1024,11 +1024,11 @@ static void amdfam10_domain_scan_bus(device_t dev)
int i;
struct bus *link;
/* Unmap all of the HT chains */
- for(reg = 0xe0; reg <= 0xec; reg += 4) {
+ for (reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
- for(link = dev->link_list; link; link = link->next) {
+ for (link = dev->link_list; link; link = link->next) {
link->secondary = dev->bus->subordinate;
pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff);
dev->bus->subordinate = link->subordinate;
@@ -1038,7 +1038,7 @@ static void amdfam10_domain_scan_bus(device_t dev)
* Including enabling relaxed ordering if it is safe.
*/
get_fx_devs();
- for(i = 0; i < fx_devs; i++) {
+ for (i = 0; i < fx_devs; i++) {
device_t f0_dev;
f0_dev = __f0_dev[i];
if (f0_dev && f0_dev->enabled) {
@@ -1348,7 +1348,7 @@ static void sysconf_init(device_t dev) // first node
unsigned ht_c_index;
- for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
+ for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
sysconf.ht_c_conf_bus[ht_c_index] = 0;
}
@@ -1370,8 +1370,8 @@ static void sysconf_init(device_t dev) // first node
sysconf.enabled_apic_ext_id = 1;
}
#if (CONFIG_APIC_ID_OFFSET>0)
- if(sysconf.enabled_apic_ext_id) {
- if(sysconf.bsp_apicid == 0) {
+ if (sysconf.enabled_apic_ext_id) {
+ if (sysconf.bsp_apicid == 0) {
/* bsp apic id is not changed */
sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
} else {
@@ -1452,7 +1452,7 @@ static void cpu_bus_scan(device_t dev)
nb_cfg_54 = 0;
ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
- if(ApicIdCoreIdSize) {
+ if (ApicIdCoreIdSize) {
siblings = (1<<ApicIdCoreIdSize)-1;
} else {
siblings = 3; //quad core
@@ -1468,10 +1468,10 @@ static void cpu_bus_scan(device_t dev)
#if CONFIG_CBB
dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
- if(dev_mc && dev_mc->bus) {
+ if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if(pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
@@ -1482,17 +1482,17 @@ static void cpu_bus_scan(device_t dev)
printk(BIOS_DEBUG, "\n");
}
dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
- if(!dev_mc) {
+ if (!dev_mc) {
dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if(pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
- if((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
+ if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
- while(dev_mc){
+ while (dev_mc){
printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
@@ -1516,8 +1516,8 @@ static void cpu_bus_scan(device_t dev)
nodes = sysconf.nodes;
#if CONFIG_CBB && (NODE_NUMS > 32)
- if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe
- if(pci_domain->link_list && !pci_domain->link_list->next) {
+ if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (pci_domain->link_list && !pci_domain->link_list->next) {
struct bus *new_link = new_link(pci_domain);
pci_domain->link_list->next = new_link;
new_link->link_num = 1;
@@ -1540,7 +1540,7 @@ static void cpu_bus_scan(device_t dev)
if (disable_cu_siblings)
printk(BIOS_DEBUG, "Disabling siblings on each compute unit as requested\n");
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
device_t cdb_dev;
unsigned busn, devn;
struct bus *pbus;
@@ -1556,7 +1556,7 @@ static void cpu_bus_scan(device_t dev)
devn = CONFIG_CDB+i;
pbus = dev_mc->bus;
#if CONFIG_CBB && (NODE_NUMS > 32)
- if(i>=32) {
+ if (i>=32) {
busn--;
devn-=32;
pbus = pci_domain->link_list->next;
@@ -1570,7 +1570,7 @@ static void cpu_bus_scan(device_t dev)
* ensure all of the cpu's pci devices are found.
*/
int fn;
- for(fn = 0; fn <= 5; fn++) { //FBDIMM?
+ for (fn = 0; fn <= 5; fn++) { //FBDIMM?
cdb_dev = pci_probe_dev(NULL, pbus,
PCI_DEVFN(devn, fn));
}
@@ -1630,7 +1630,7 @@ static void cpu_bus_scan(device_t dev)
siblings = cores_found;
u32 jj;
- if(disable_siblings) {
+ if (disable_siblings) {
jj = 0;
} else
{
@@ -1665,7 +1665,7 @@ static void cpu_bus_scan(device_t dev)
}
#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
- if(sysconf.enabled_apic_ext_id) {
+ if (sysconf.enabled_apic_ext_id) {
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
apic_id += sysconf.apicid_offset;
}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 6166169812..6d063ab522 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -644,7 +644,7 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
struct sys_info *sysinfo = &sysinfo_car;
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
- for(j=0;j<DIMM_SOCKETS;j++) {
+ for (j=0;j<DIMM_SOCKETS;j++) {
pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
}
diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
index 6450dd8b3c..df3850b87f 100644
--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
@@ -35,12 +35,12 @@ static u32 get_htic_bit(u8 i, u8 bit)
static void wait_till_sysinfo_in_ram(void)
{
- while(1) {
+ while (1) {
/* give the NB a break, many CPUs spinning on one bit makes a
* lot of traffic and time is not too important to APs.
*/
udelay(1000);
- if(get_htic_bit(0, 9)) return;
+ if (get_htic_bit(0, 9)) return;
}
}
#endif
@@ -56,7 +56,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
int j;
int index = 0;
struct mem_controller *ctrl;
- for(i=0;i<controllers; i++) {
+ for (i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = NODE_PCI(i, 0);
@@ -66,11 +66,11 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
ctrl->f4 = NODE_PCI(i, 4);
ctrl->f5 = NODE_PCI(i, 5);
- if(spd_addr == (void *)0) continue;
+ if (spd_addr == (void *)0) continue;
ctrl->spd_switch_addr = spd_addr[index++];
- for(j=0; j < 8; j++) {
+ for (j=0; j < 8; j++) {
ctrl->spd_addr[j] = spd_addr[index++];
}
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 0ed4ffdf85..bdf70b56b2 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -90,7 +90,7 @@ void set_bios_reset(void)
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i,0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
@@ -110,7 +110,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
// put node and link in correct bit
val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ;
- for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ for (reg = 0xE0; reg < 0xF0; reg += 0x04) {
u32 config_map;
config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg);
if ((config_map & 3) != 3) {
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index cd2f71302e..a14fc3c842 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -22,7 +22,7 @@ static void setup_resource_map(const u32 *register_values, u32 max)
u32 i;
// printk(BIOS_DEBUG, "setting up resource map....");
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
device_t dev;
u32 where;
u32 reg;
@@ -42,7 +42,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
{
u32 i;
// printk(BIOS_DEBUG, "setting up resource map offset....");
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
device_t dev;
u32 where;
unsigned long reg;
@@ -68,7 +68,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
if (IS_ENABLED(RES_DEBUG))
printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
- for(i = 0; i < max; i += 4) {
+ for (i = 0; i < max; i += 4) {
if (IS_ENABLED(RES_DEBUG))
printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i/4, register_values[i],
@@ -140,7 +140,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
if (IS_ENABLED(RES_DEBUG))
printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
- for(i = 0; i < max; i += 4) {
+ for (i = 0; i < max; i += 4) {
if (IS_ENABLED(RES_DEBUG))
printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
@@ -194,7 +194,7 @@ static void setup_iob_resource_map(const u32 *register_values, u32 max)
{
u32 i;
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
u32 where;
u32 reg;
@@ -210,7 +210,7 @@ static void setup_io_resource_map(const u32 *register_values, u32 max)
{
u32 i;
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
u32 where;
u32 reg;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 03:08:50 +0000