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-rw-r--r--src/northbridge/amd/amdmct/amddefs.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 9d3e86a2a1..58f43f1500 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -13,6 +13,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+#ifndef AMDDEFS_H
+#define AMDDEFS_H
/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */
@@ -163,3 +165,29 @@
#define AMD_PKGTYPE_ASB2 4
#define AMD_PKGTYPE_C32 5
#define AMD_PKGTYPE_FM2 6
+
+//DDR2 REG and unbuffered : Socket F 1027 and AM3
+/* every channel have 4 DDR2 DIMM for socket F
+ * 2 for socket M2/M3
+ * 1 for socket s1g1
+ */
+#define DIMM_SOCKETS 4
+struct mem_controller {
+ u32 node_id;
+ pci_devfn_t f0, f1, f2, f3, f4, f5;
+ /* channel0 is DCT0 --- channelA
+ * channel1 is DCT1 --- channelB
+ * can be ganged, a single dual-channel DCT ---> 128 bit
+ * or unganged a two single-channel DCTs ---> 64bit
+ * When the DCTs are ganged, the writes to DCT1 set of registers
+ * (F2x1XX) are ignored and reads return all 0's
+ * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
+ * and all the associated indexed registers, are still
+ * independently accessiable
+ */
+ /* FIXME: I will only support ganged mode for easy support */
+ u8 spd_switch_addr;
+ u8 spd_addr[DIMM_SOCKETS*2];
+};
+
+#endif