diff options
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
-rw-r--r-- | src/northbridge/amd/amdmct/mct/Makefile.inc | 16 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 29 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.h | 47 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d_gcc.c | 351 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 368 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctardk3.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctardk4.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctchi_d.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctcsi_d.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 28 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mcthdi.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctpro_d.c | 15 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc.c | 10 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 |
16 files changed, 479 insertions, 398 deletions
diff --git a/src/northbridge/amd/amdmct/mct/Makefile.inc b/src/northbridge/amd/amdmct/mct/Makefile.inc new file mode 100644 index 0000000000..f986201c6d --- /dev/null +++ b/src/northbridge/amd/amdmct/mct/Makefile.inc @@ -0,0 +1,16 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +# DDR2 +romstage-y += mct_d.c mct_d_gcc.c mctcsi_d.c mctmtr_d.c mctecc_d.c +romstage-y += mctpro_d.c mctdqs_d.c mctsrc.c mctsrc1p.c mcttmrl.c +romstage-y += mcthdi.c mctndi_d.c mctchi_d.c + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x10) +romstage-y += mctardk3.c +endif + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) +romstage-y += mctardk4.c +endif + +endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626e8a..73aa20b329 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,6 +33,8 @@ * supported. */ +#include "mct_d.h" + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -41,15 +43,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void StartupDCT_D(struct MCTStatStruc *pMCTstat, @@ -66,6 +61,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); +static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void StitchMemory_D(struct MCTStatStruc *pMCTstat, @@ -81,8 +78,6 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void mct_DramInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); static void Get_Trdrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); @@ -175,7 +170,9 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; -static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; + +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -661,7 +658,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, } -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -693,7 +690,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, } -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 val; @@ -716,7 +713,7 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, } -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* Ensures that memory clear has completed on all node.*/ @@ -768,7 +765,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } -static u8 NodePresent_D(u8 Node) +u8 NodePresent_D(u8 Node) { /* * Determine if a single Hammer Node exists within the network. @@ -3655,7 +3652,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, } -static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax @@ -3907,7 +3904,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } -static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 dev = pDCTstat->dev_dct; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909472..75c4d6278e 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -20,7 +20,18 @@ #ifndef MCT_D_H #define MCT_D_H +#define DQS_TRAIN_DEBUG 0 +#include <inttypes.h> +#include "mct_d_gcc.h" +#include <console/console.h> +#include <northbridge/amd/amdfam10/debug.h> +#include <northbridge/amd/amdfam10/raminit.h> + +extern const u8 Table_DQSRcvEn_Offset[]; +extern const u32 TestPattern0_D[]; +extern const u32 TestPattern1_D[]; +extern const u32 TestPattern2_D[]; /*=========================================================================== CPU - K8/FAM10 @@ -689,6 +700,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */ +#include <northbridge/amd/amdfam10/amdfam10.h> + /*=============================================================================== CBMEM storage ===============================================================================*/ @@ -735,9 +748,6 @@ void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void mctSMBhub_Init(u32 node); -int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -753,4 +763,35 @@ u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); void EarlySampleSupport_D(void); + +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 *dqs_pos); +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled); +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 DQSDelay, + u8 ChipSel, u8 *result); +void proc_IOCLFLUSH_D(u32 addr_hi); +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u32 TestAddr, u8 pattern); +u8 NodePresent_D(u8 Node); +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void print_debug_dqs(const char *str, u32 val, u8 level); +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); +u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); +void SetTargetWTIO_D(u32 TestAddr); +void ResetTargetWTIO_D(void); +u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 Channel, + u8 receiver, u8 *valid); #endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c new file mode 100644 index 0000000000..59618f6cc0 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mct_d_gcc.h" + +inline void _WRMSR(u32 addr, u32 lo, u32 hi) +{ + __asm__ volatile ( + "wrmsr" + : + :"c"(addr),"a"(lo), "d" (hi) + ); +} + + +inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdmsr" + :"=a"(*lo), "=d" (*hi) + :"c"(addr) + ); +} + + +inline void _RDTSC(u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdtsc" + : "=a" (*lo), "=d"(*hi) + ); +} + + +inline void _cpu_id(u32 addr, u32 *val) +{ + __asm__ volatile( + "cpuid" + : "=a" (val[0]), + "=b" (val[1]), + "=c" (val[2]), + "=d" (val[3]) + : "0" (addr)); + +} + + +u32 bsr(u32 x) +{ + u8 i; + u32 ret = 0; + + for (i = 31; i > 0; i--) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; + +} + + +u32 bsf(u32 x) +{ + u8 i; + u32 ret = 32; + + for (i = 0; i < 32; i++) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; +} + +#define _MFENCE asm volatile ("mfence") + +#define _SFENCE asm volatile ("sfence") + +/* prevent speculative execution of following instructions */ +#define _EXECFENCE asm volatile ("outb %al, $0xed") + +#include <cpu/x86/cr.h> + +void proc_CLFLUSH(u32 addr_hi) +{ + SetUpperFSbase(addr_hi); + + __asm__ volatile ( + /* clflush fs:[eax] */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:(%0)\n\t" + "mfence\n\t" + ::"a" (addr_hi<<8) + ); +} + + +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) +{ + __asm__ volatile ( + /*prevent speculative execution of following instructions*/ + /* FIXME: needed ? */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + ); + +} + + +u32 read32_fs(u32 addr_lo) +{ + u32 value; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + return value; +} + +#ifdef UNUSED_CODE +static u8 read8_fs(u32 addr_lo) +{ + u8 byte; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movb %%fs:(%1), %b0\n\t" + "mfence\n\t" + :"=b"(byte): "a" (addr_lo) + ); + return byte; +} +#endif + +void FlushDQSTestPattern_L9(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "a"(addr_lo+128+4*64) + ); + +} + + +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" + + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" + + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "a"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); +} + +void ReadL18TestPattern(u32 addr_lo) +{ + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "movl %%fs:64(%%esi), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edi), %%eax\n\t" //+4 + "movl %%fs:-64(%%edi), %%eax\n\t" //+5 + "movl %%fs:(%%edi), %%eax\n\t" //+6 + "movl %%fs:64(%%edi), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 + "movl %%fs:(%%ebx), %%eax\n\t" //+10 + "movl %%fs:64(%%ebx), %%eax\n\t" //+11 + + "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 + "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 + "movl %%fs:(%%ecx), %%eax\n\t" //+14 + "movl %%fs:64(%%ecx), %%eax\n\t" //+15 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+16 + "movl %%fs:-64(%%edx), %%eax\n\t" //+17 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "S"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); + +} + +void ReadL9TestPattern(u32 addr_lo) +{ + + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + + "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 + "movl %%fs:(%%ecx), %%eax\n\t" //+2 + "movl %%fs:64(%%ecx), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+4 + "movl %%fs:-64(%%edx), %%eax\n\t" //+5 + "movl %%fs:(%%edx), %%eax\n\t" //+6 + "movl %%fs:64(%%edx), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "d"(addr_lo+128+4*64) + ); + +} + +void ReadMaxRdLat1CLTestPattern_D(u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "mfence\n\t" + :: "a"(0), "S"((addr<<8)+128) + ); + +} + +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) + ); +} + +void FlushMaxRdLatTestPattern_D(u32 addr) +{ + /* Flush a pattern of 72 bit times (per DQ) from cache. + * This procedure is used to ensure cache miss on the next read training. + */ + + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line + "clflush %%fs:-64(%%esi)\n\t" //+1 + "clflush %%fs:(%%esi)\n\t" //+2 + "mfence\n\t" + + :: "S"((addr<<8)+128) + ); +} + +u32 stream_to_int(u8 const *p) +{ + int i; + u32 val; + u32 valx; + + val = 0; + + for (i = 3; i >= 0; i--) { + val <<= 8; + valx = *(p+i); + val |= valx; + } + + return val; +} + +u8 oemNodePresent_D(u8 Node, u8 *ret) +{ + *ret = 0; + return 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fbfe988ab2..0b9a7d19f1 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -13,362 +13,36 @@ * GNU General Public License for more details. */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H -static inline void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} +#include <inttypes.h> - -static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - - -static inline void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - - -static inline void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - - -static u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; - -} - - -static u32 bsf(u32 x) -{ - u8 i; - u32 ret = 32; - - for (i = 0; i < 32; i++) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; -} +void _WRMSR(u32 addr, u32 lo, u32 hi); +void _RDMSR(u32 addr, u32 *lo, u32 *hi); +void _RDTSC(u32 *lo, u32 *hi); +void _cpu_id(u32 addr, u32 *val); +u32 bsr(u32 x); +u32 bsf(u32 x); #define _MFENCE asm volatile ("mfence") - #define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -#include <cpu/x86/cr.h> - u32 SetUpperFSbase(u32 addr_hi); +void proc_CLFLUSH(u32 addr_hi); +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); +u32 read32_fs(u32 addr_lo); +void FlushDQSTestPattern_L9(u32 addr_lo); +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); +void ReadL18TestPattern(u32 addr_lo); +void ReadL9TestPattern(u32 addr_lo); +void ReadMaxRdLat1CLTestPattern_D(u32 addr); +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); +void FlushMaxRdLatTestPattern_D(u32 addr); +u32 stream_to_int(u8 const *p); +u8 oemNodePresent_D(u8 Node, u8 *ret); - -static void proc_CLFLUSH(u32 addr_hi) -{ - SetUpperFSbase(addr_hi); - - __asm__ volatile ( - /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" - "mfence\n\t" - ::"a" (addr_hi<<8) - ); -} - - -static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) -{ - __asm__ volatile ( - /*prevent speculative execution of following instructions*/ - /* FIXME: needed ? */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) - ); - -} - - -static u32 read32_fs(u32 addr_lo) -{ - u32 value; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - return value; -} - -#ifdef UNUSED_CODE -static u8 read8_fs(u32 addr_lo) -{ - u8 byte; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movb %%fs:(%1), %b0\n\t" - "mfence\n\t" - :"=b"(byte): "a" (addr_lo) - ); - return byte; -} #endif - -static void FlushDQSTestPattern_L9(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "a"(addr_lo+128+4*64) - ); - -} - - -static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" - - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" - - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "a"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); -} - - -static void ReadL18TestPattern(u32 addr_lo) -{ - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "movl %%fs:64(%%esi), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edi), %%eax\n\t" //+4 - "movl %%fs:-64(%%edi), %%eax\n\t" //+5 - "movl %%fs:(%%edi), %%eax\n\t" //+6 - "movl %%fs:64(%%edi), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 - "movl %%fs:(%%ebx), %%eax\n\t" //+10 - "movl %%fs:64(%%ebx), %%eax\n\t" //+11 - - "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 - "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 - "movl %%fs:(%%ecx), %%eax\n\t" //+14 - "movl %%fs:64(%%ecx), %%eax\n\t" //+15 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+16 - "movl %%fs:-64(%%edx), %%eax\n\t" //+17 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "S"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); - -} - - -static void ReadL9TestPattern(u32 addr_lo) -{ - - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 - "movl %%fs:(%%ecx), %%eax\n\t" //+2 - "movl %%fs:64(%%ecx), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+4 - "movl %%fs:-64(%%edx), %%eax\n\t" //+5 - "movl %%fs:(%%edx), %%eax\n\t" //+6 - "movl %%fs:64(%%edx), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "d"(addr_lo+128+4*64) - ); - -} - - -static void ReadMaxRdLat1CLTestPattern_D(u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) - ); - -} - - -static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) - ); -} - - -static void FlushMaxRdLatTestPattern_D(u32 addr) -{ - /* Flush a pattern of 72 bit times (per DQ) from cache. - * This procedure is used to ensure cache miss on the next read training. - */ - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line - "clflush %%fs:-64(%%esi)\n\t" //+1 - "clflush %%fs:(%%esi)\n\t" //+2 - "mfence\n\t" - - :: "S"((addr<<8)+128) - ); -} - - -static u32 stream_to_int(u8 const *p) -{ - int i; - u32 val; - u32 valx; - - val = 0; - - for (i = 3; i >= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - - -#ifdef UNUSED_CODE -static void oemSet_NB32(u32 addr, u32 val, u8 *valid) -{ -} - - -static u32 oemGet_NB32(u32 addr, u8 *valid) -{ - *valid = 0; - return 0xffffffff; -} -#endif - - -static u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index e2903337f9..fe57d31f05 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL); diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 8815943c72..b35f7baa07 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index 705bd915f4..d2acc15118 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ - +#include "mct_d.h" void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 1c86239cfc..6a19788ab3 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" /* Low swap bit vs bank size encoding (physical, not logical address bit) * ;To calculate the number by hand, add the number of Bank address bits diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 63631623cf..ec77c490d7 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> +#include <cpu/amd/mtrr.h> static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -38,30 +41,20 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, u32 addr_lo); static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo); -static void SetTargetWTIO_D(u32 TestAddr); -static void ResetTargetWTIO_D(void); static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr_lo); -void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 cs_start); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 receiver, u8 *valid); static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 *buffer); -#define DQS_TRAIN_DEBUG 0 - -static void print_debug_dqs(const char *str, u32 val, u8 level) +void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -70,7 +63,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level) #endif } -static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -193,9 +186,6 @@ static const u32 TestPatternJD1b_D[] = { 0x80808080,0x80808080,0x80808080,0x80808080 /* QW7,CHA-B, DQ7-ODD */ }; -const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11}; - - void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass) { @@ -653,7 +643,7 @@ static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat, } -static void proc_IOCLFLUSH_D(u32 addr_hi) +void proc_IOCLFLUSH_D(u32 addr_hi) { SetTargetWTIO_D(addr_hi); proc_CLFLUSH(addr_hi); @@ -820,7 +810,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, } } -static void SetTargetWTIO_D(u32 TestAddr) +void SetTargetWTIO_D(u32 TestAddr) { u32 lo, hi; hi = TestAddr >> 24; @@ -832,7 +822,7 @@ static void SetTargetWTIO_D(u32 TestAddr) } -static void ResetTargetWTIO_D(void) +void ResetTargetWTIO_D(void) { u32 lo, hi; @@ -1173,7 +1163,7 @@ exitGetAddr: } -static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr, u8 pattern) { diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c index d9d87af82e..b67282ef60 100644 --- a/src/northbridge/amd/amdmct/mct/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct/mcthdi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 389d56b77f..3f09f4a472 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ - +#include "mct_d.h" void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 6802a76dec..0acb6f4ff4 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include "mct_d.h" + void EarlySampleSupport_D(void) { } @@ -321,7 +323,7 @@ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) } #endif -static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 DQSDelay, u8 ChipSel, u8 *result) { @@ -365,12 +367,6 @@ u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) } -static void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { - - if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) - *enabled = 0; -} - #ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { @@ -394,3 +390,8 @@ void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } + +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { + if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) + *enabled = 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a87cea81c0..3b7cff87db 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> + /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT ******************************************************************************/ @@ -43,22 +46,21 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); - /* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -static const u32 TestPattern0_D[] = { +const u32 TestPattern0_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -static const u32 TestPattern1_D[] = { +const u32 TestPattern1_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -static const u32 TestPattern2_D[] = { +const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index bfd103b311..31a3a5d21f 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) { diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 1095259238..67397fc83a 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> /* * Description: Max Read Latency Training feature for DDR 2 MCT |