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-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c2
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c31
3 files changed, 17 insertions, 20 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 0c37366845..08d8d43ff3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2398,10 +2398,10 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec
tsc_msr = rdmsr(0x00000010);
start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
- do {
+ do {
tsc_msr = rdmsr(0x00000010);
current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
- } while ((current_timestamp - start_timestamp) < cycle_count);
+ } while ((current_timestamp - start_timestamp) < cycle_count);
}
static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 324e35e980..802417971f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -930,7 +930,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
*/
for (lane = 0; lane < 8; lane++) {
if (trained[lane]) {
- pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
+ pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
} else {
printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 0ba2d33a7f..143468a7e4 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -476,34 +476,31 @@ static void mctHookAfterDramInit(void)
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
static void vErratum372(struct DCTStatStruc *pDCTstat)
{
- msr_t msr = rdmsr(NB_CFG_MSR);
+ msr_t msr = rdmsr(NB_CFG_MSR);
int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32)));
- // is this the right way to check for NB pstate 1 or DDR3-1333 ?
- if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
- &&(!pDCTstat->GangedMode)) {
- /* DisableCf8ExtCfg */
- msr.hi &= ~(3 << (51 - 32));
- wrmsr(NB_CFG_MSR, msr);
- }
+ // is this the right way to check for NB pstate 1 or DDR3-1333 ?
+ if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+ &&(!pDCTstat->GangedMode)) {
+ /* DisableCf8ExtCfg */
+ msr.hi &= ~(3 << (51 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+ }
}
static void vErratum414(struct DCTStatStruc *pDCTstat)
{
- int dct=0;
- for (; dct < 2 ; dct++)
- {
- int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
+ int dct=0;
+ for (; dct < 2 ; dct++) {
+ int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
int powerDown = dRAMConfigHi & (1 << PowerDownEn );
int ddr3 = dRAMConfigHi & (1 << Ddr3Mode );
- int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
+ int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel);
- if (powerDown && ddr3 && pchgPDModeSel )
- {
- Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
+ if (powerDown && ddr3 && pchgPDModeSel )
+ Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
}
- }
}
#endif