diff options
Diffstat (limited to 'src/northbridge/amd/gx2/raminit.c')
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index e45d696e35..b1cb1af6b3 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -21,13 +21,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(0x2000001a); msr.lo = 0x0101; wrmsr(0x2000001a, msr); - //print_debug("sdram_enable step 2\r\n"); + //print_debug("sdram_enable step 2\n"); /* 3. release CKE mask to enable CKE */ msr = rdmsr(0x2000001d); msr.lo &= ~(0x03 << 8); wrmsr(0x2000201d, msr); - //print_debug("sdram_enable step 3\r\n"); + //print_debug("sdram_enable step 3\n"); /* 4. set and clear REF_TST 16 times, more shouldn't hurt * why this is before EMRS and MRS ? */ @@ -38,7 +38,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x01 << 3); wrmsr(0x20000018, msr); } - //print_debug("sdram_enable step 4\r\n"); + //print_debug("sdram_enable step 4\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -50,7 +50,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x03 << 6); msr.lo |= (0x00 << 6); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 5\r\n"); + //print_debug("sdram_enable step 5\n"); /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -58,7 +58,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 28) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 6\r\n"); + //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, * it is documented in LX datasheet */ @@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 27) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 7\r\n"); + //print_debug("sdram_enable step 7\n"); /* 8. load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~0x01; wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 8\r\n"); + //print_debug("sdram_enable step 8\n"); /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) @@ -107,7 +107,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* make sure there is nothing stale in the cache */ __asm__("wbinvd\n"); - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { |