diff options
Diffstat (limited to 'src/northbridge/amd/gx2')
| -rw-r--r-- | src/northbridge/amd/gx2/chipsetinit.c | 30 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/grphinit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 26 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/northbridgeinit.c | 84 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 26 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 8 |
6 files changed, 88 insertions, 88 deletions
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 620f56452d..f0b99e7e9d 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -61,7 +61,7 @@ static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { #ifdef UNUSED_CODE struct acpiinit { - unsigned short ioreg; + unsigned short ioreg; unsigned long regdata; unsigned short iolen; }; @@ -116,21 +116,21 @@ static void pmChipsetInit(void) port = (PMLogic_BASE + 0x034); val = 0x0A0 ; /* 5ms*/ outl(val, port); - + /* PM_WKD*/ port = (PMLogic_BASE + 0x030); outl(val, port); - + /* PM_SED*/ port = (PMLogic_BASE + 0x014); val = 0x04601 ; /* 5ms*/ outl(val, port); - + /* PM_SIDD*/ port = (PMLogic_BASE + 0x020); val = 0x08C02 ; /* 10ms*/ outl(val, port); - + /* GPIO24 OUT_AUX1 function is the external signal for 5535's * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem @@ -154,7 +154,7 @@ static void pmChipsetInit(void) * Programming of GPIO11 will be done by VSA PM code. During VSA * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks * should be On or Off. This is based on a Setup item. We do not want - * to leave GPIO11 enabled because of a Hawk board problem. With + * to leave GPIO11 enabled because of a Hawk board problem. With * GPIO11 enabled in S3, something is back-driving GPIO11 causing it * to float to 1.6-1.7V. */ @@ -188,7 +188,7 @@ static uint32_t FlashPort[] = { * ChipsetFlashSetup * * Flash LBARs need to be setup before VSA init so the PCI BARs have - * correct size info. Call this routine only if flash needs to be + * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). * **************************************************************************/ @@ -240,16 +240,16 @@ static void ChipsetFlashSetup(void) } - + /**************************************************************************** - * + * * ChipsetGeodeLinkInit * * Handle chipset specific GeodeLink settings here. * Called from GeodeLink init code. - * + * ****************************************************************************/ -static void +static void ChipsetGeodeLinkInit(void) { msr_t msr; @@ -269,7 +269,7 @@ ChipsetGeodeLinkInit(void) return; totalmem = sizeram() << 20 - 1; - totalmem >>= 12; + totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff; msr.lo = totalmem; @@ -292,7 +292,7 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); #ifdef UNUSED_CODE - /* we hope NEVER to be in coreboot when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; @@ -319,14 +319,14 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) msrnum = MSR_SB_USB2 + 8; wrmsr(msrnum, msr); } - + /* set hd IRQ */ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); /* Allow IO read and writes during a ATA DMA operation. */ /* This could be done in the HD rom but do it here for easier debugging. */ - + msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index a30ba78373..e59a838afe 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -4,7 +4,7 @@ #include <device/device.h> #include "chip.h" #include "northbridge.h" - + // FIXME handle UMA properly. #define VIDEO_MB 8 // MB of video memory diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e74a8e33f8..98acbc9f95 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -19,7 +19,7 @@ #define NORTHBRIDGE_FILE "northbridge.c" -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int @@ -128,7 +128,7 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); /* The IRQ steering values (in hex) are effectively dcba, where: - * <a> represents the IRQ for INTA, + * <a> represents the IRQ for INTA, * <b> represents the IRQ for INTB, * <c> represents the IRQ for INTC, and * <d> represents the IRQ for INTD. @@ -146,10 +146,10 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { /* * setup_gx2_cache * - * Returns the amount of memory (in KB) available to the system. This is the + * Returns the amount of memory (in KB) available to the system. This is the * total amount of memory less the amount of memory reserved for SMM use. * - */ + */ static int setup_gx2_cache(void) { @@ -200,13 +200,13 @@ setup_gx2(void) membytes = size_kb * 1024; /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! - * so it is safe to use. You should NOT at this point call - * sizeram() directly. + * so it is safe to use. You should NOT at this point call + * sizeram() directly. */ /* we need to set 0x10000028 and 0x40000029 */ /* - * These two descriptors cover the range from 1 MB (0x100000) to + * These two descriptors cover the range from 1 MB (0x100000) to * SYSTOP (a.k.a. TOM, or Top of Memory) */ @@ -271,16 +271,16 @@ setup_gx2(void) static void enable_shadow(device_t dev) { - + } -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { unsigned long m; struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); - + enable_shadow(dev); irq_init_steering(dev, nb->irqmap); @@ -421,7 +421,7 @@ static void pci_domain_set_resources(device_t dev) continue; ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); } - + tomk = ramreg << 10; /* Sort out the framebuffer size */ @@ -455,7 +455,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -516,5 +516,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_amd_gx2_ops = { CHIP_NAME("AMD GX (previously GX2) Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 4ad5af23bc..7053f5e5d9 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -126,14 +126,14 @@ ShadowInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); if (msr.lo == 0) { - writeglmsr(gl); + writeglmsr(gl); } } -/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. +/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. * CLEAN ME UP */ -/* yes, this duplicates later code, but it seems that is how they want it done. +/* yes, this duplicates later code, but it seems that is how they want it done. */ static void SysmemInit(struct gliutable *gl) @@ -141,8 +141,8 @@ SysmemInit(struct gliutable *gl) msr_t msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* + * Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -165,7 +165,7 @@ SysmemInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL0Init(struct gliutable *gl) { @@ -188,11 +188,11 @@ DMMGL0Init(struct gliutable *gl) { msr.hi |= (DMM_OFFSET >> 24); msr.lo = DMM_OFFSET << 8; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL1Init(struct gliutable *gl) { @@ -211,7 +211,7 @@ DMMGL1Init(struct gliutable *gl) { /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */ printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -238,7 +238,7 @@ SMMGL0Init(struct gliutable *gl) { msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -254,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) { msr.hi |= (SMM_OFFSET >> 24); msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -265,31 +265,31 @@ GLIUInit(struct gliutable *gl){ while (gl->desc_type != GL_END){ switch(gl->desc_type){ - default: + default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); case SC_SHADOW: /* Check for a Shadow entry*/ ShadowInit(gl); break; - + case R_SYSMEM: /* check for a SYSMEM entry*/ SysmemInit(gl); break; - + case BMO_DMM: /* check for a DMM entry*/ DMMGL0Init(gl); break; - + case BM_DMM : /* check for a DMM entry*/ DMMGL1Init(gl); break; - + case BMO_SMM : /* check for a SMM entry*/ SMMGL0Init(gl); break; - + case BM_SMM : /* check for a SMM entry*/ - SMMGL1Init(gl); + SMMGL1Init(gl); break; } gl++; @@ -413,7 +413,7 @@ static void GLPCIInit(void){ /* */ /* 5535 NB Init*/ - /* */ + /* */ msrnum = GLPCI_ARB; msr = rdmsr(msrnum); msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; @@ -432,19 +432,19 @@ static void GLPCIInit(void){ msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; wrmsr(msrnum, msr); @@ -478,7 +478,7 @@ static void GLPCIInit(void){ /* * Modified:*/ /* **/ /* ***************************************************************************/ -static void +static void ClockGatingInit (void){ msr_t msr; struct msrinit *gating = ClockGatingDefault; @@ -489,7 +489,7 @@ ClockGatingInit (void){ NOSTACK bx, GetNVRAMValueBX cmp al, TVALUE_CG_OFF je gatingdone - + cmp al, TVALUE_CG_DEFAULT jb allon ja performance @@ -517,7 +517,7 @@ performance: } -static void +static void GeodeLinkPriority(void){ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; @@ -537,7 +537,7 @@ GeodeLinkPriority(void){ } - + /* * Get the GLIU0 shadow register settings * If the setShadow function is used then all shadow descriptors @@ -613,7 +613,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; - + // Set the Enable Register. msr = rdmsr(GLPCI_REN); @@ -667,7 +667,7 @@ static void setShadow(uint64_t shadowSettings) * Destroys: * **************************************************************************/ -static void +static void shadowRom(void) { uint64_t shadowSettings = getShadow(); @@ -688,7 +688,7 @@ shadowRom(void) * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 @@ -716,17 +716,17 @@ RCONFInit(void) while (1); } -// sysdescfound: +// sysdescfound: /* found the descriptor... get its contents */ msr = rdmsr(gl->desc_name); - /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the - * top 8 bits go into 0-7 of edx. + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - + // Set Default SYSMEM region properties msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8) @@ -739,7 +739,7 @@ RCONFInit(void) // Set ROMBASE cache properties. msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - + // now program RCONF_DEFAULT wrmsr(CPU_RCONF_DEFAULT, msr); @@ -776,15 +776,15 @@ northbridgeinit(void) GLIUInit(gliutables[i]); GeodeLinkPriority(); - + shadowRom(); - - // GeodeROM ensures that the BIOS waits the required 1 second before + + // GeodeROM ensures that the BIOS waits the required 1 second before // allowing anything to access PCI // PCIDelay(); - + RCONFInit(); - + // The cacheInit function in GeodeROM tests cache and, among other things, // makes sure all INVD instructions are treated as WBINVD. We do this // because we've found some programs which require this behavior. @@ -792,7 +792,7 @@ northbridgeinit(void) msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; wrmsr(CPU_DM_CONFIG0, msr); - + /* Now that the descriptor to memory is set up.*/ /* The memory controller needs one read to synch its lines before it can be used.*/ i = *(int *) 0; diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 898e31dcd4..c1b22a28a0 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -125,7 +125,7 @@ static unsigned int get_memory_speed(void) #define DEFAULT_MDIV 3 #define DEFAULT_VDIV 2 -#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 +#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 static void pll_reset(void) { @@ -134,10 +134,10 @@ static void pll_reset(void) unsigned SyncBits; // store the sync bits in up ebx // clear the Bypass bit - + // If the straps say we are in bypass and the syspll is not AND there are no software // bits set then FS2 or something set up the PLL and we should not change it. - + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -145,15 +145,15 @@ static void pll_reset(void) // If the "we've already been here" flag is set, don't reconfigure the pll if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) ) { // we haven't configured the PLL; do it now - + // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the // correct Strap Table. post_code(POST_PLL_INIT); - + // configure for DDR msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // Use Manual settings // UseManual: post_code(POST_PLL_MANUAL); @@ -161,7 +161,7 @@ static void pll_reset(void) // DIV settings manually entered. // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // use gs and fs since we don't need them. - + // ProgramClocks: // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // move everything into ebx @@ -174,7 +174,7 @@ static void pll_reset(void) // FbDIV MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT); - // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values + // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -192,15 +192,15 @@ static void pll_reset(void) // Check for Bypass mode. if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET) { - // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. + // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET; } else { - // CheckPCIsync: + // CheckPCIsync: // If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater // look up the real divider... if we get a 0 we have serious problems - if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % + if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) ) { SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET; @@ -234,13 +234,13 @@ static void pll_reset(void) msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET); msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // You should never get here..... The chip has reset. post_code(POST_PLL_RESET_FAIL); while (1); } // we haven't configured the PLL; do it now - + } // End of Goodrich version of pll_reset /////////////////////////////////////////////////////////////////////////////// diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index b1cb1af6b3..3f99cab8ee 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -61,7 +61,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, - * it is documented in LX datasheet */ + * it is documented in LX datasheet */ /* load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); msr.lo |= ((0x01 << 27) | 0x01); @@ -85,10 +85,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* load RDSYNC */ msr = rdmsr(0x2000001f); msr.hi = 0x000ff310; - /* the above setting is supposed to be good for "slow" ram. We have found that for - * some dram, at some clock rates, e.g. hynix at 366/244, this will actually + /* the above setting is supposed to be good for "slow" ram. We have found that for + * some dram, at some clock rates, e.g. hynix at 366/244, this will actually * cause errors. The fix is to just set it to 0x310. Tested on 3 boards - * with 3 different type of dram -- Hynix, PSC, infineon. + * with 3 different type of dram -- Hynix, PSC, infineon. * I am leaving this comment here so that at some future time nobody is tempted * to mess with this setting -- RGM, 9/2006 */ |