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-rw-r--r--src/northbridge/amd/gx2/Config.lb4
-rw-r--r--src/northbridge/amd/gx2/northbridge.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb
index 169db63065..0bba6ce9ce 100644
--- a/src/northbridge/amd/gx2/Config.lb
+++ b/src/northbridge/amd/gx2/Config.lb
@@ -1,7 +1,7 @@
-uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_WRITE_HIGH_TABLES
config chip.h
driver northbridge.o
object northbridgeinit.o
object chipsetinit.o
object grphinit.o
-default CONFIG_HAVE_HIGH_TABLES=1
+default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index f6e862a9b7..b20d3d7829 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -476,7 +476,7 @@ static struct device_operations cpu_bus_ops = {
void chipsetInit (void);
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -503,7 +503,7 @@ static void enable_dev(struct device *dev)
dev->ops = &pci_domain_ops;
pci_set_method(dev);
tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE;
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024;