summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/lx
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/Kconfig31
-rw-r--r--src/northbridge/amd/lx/pll_reset.c8
2 files changed, 34 insertions, 5 deletions
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
index c1fea495ff..d74d71554a 100644
--- a/src/northbridge/amd/lx/Kconfig
+++ b/src/northbridge/amd/lx/Kconfig
@@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX
bool
select GEODE_VSA
+if NORTHBRIDGE_AMD_LX
+
config VIDEO_MB
int
default 8
- depends on NORTHBRIDGE_AMD_LX
+
+config PLL_MANUAL_CONFIG
+ bool
+
+if PLL_MANUAL_CONFIG
+
+# "Core/GLIU Frequency"
+config CORE_GLIU_500_266
+ bool # "500MHz / 266MHz"
+
+config CORE_GLIU_500_333
+ bool # "500MHz / 333MHz"
+
+config CORE_GLIU_500_400
+ bool # "500MHz / 400MHz"
+
+config PLLMSRhi
+ hex
+ default 0x39c if CORE_GLIU_500_266
+ default 0x49c if CORE_GLIU_500_333
+ default 0x59c if CORE_GLIU_500_400
+
+config PLLMSRlo
+ hex
+
+endif
+
+endif
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 3077b61c9c..bf01e54e29 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static void pll_reset(char manualconf)
+static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
@@ -31,13 +31,13 @@ static void pll_reset(char manualconf)
if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
printk(BIOS_DEBUG, "Configuring PLL.\n");
- if (manualconf) {
+ if (CONFIG_PLL_MANUAL_CONFIG) {
post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = PLLMSRhi;
+ msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;
/* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = PLLMSRlo;
+ msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;
} else {
/*automatic configuration (straps) */
post_code(POST_PLL_STRAP);