diff options
Diffstat (limited to 'src/northbridge/amd')
24 files changed, 109 insertions, 109 deletions
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 29f42745ce..c31cb70bb0 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -424,7 +424,7 @@ static void set_resource(struct device *dev, struct resource *resource, } -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -438,7 +438,7 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9da4e8ee59..381d19843e 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -410,7 +410,7 @@ static void set_resource(struct device *dev, struct resource *resource, report_resource_stored(dev, resource, buf); } -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -424,7 +424,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7a75997963..367fecafa5 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -367,7 +367,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index ddfab82e78..44f49ea094 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -366,7 +366,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 9840c1c73c..fea097f6c6 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -32,7 +32,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { AGESA_STATUS status; - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + if (CONFIG(ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); if (status == AGESA_SUCCESS) Post->MemConfig.MemRestoreCtl = 1; diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 43b205a14d..93625fce12 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -20,7 +20,7 @@ #include <AGESA.h> #include <AMD.h> -#define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER) /* eventlog */ const char *agesa_struct_name(int state); @@ -30,7 +30,7 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); /* For suspend-to-ram support. */ -#if !IS_ENABLED(CONFIG_CPU_AMD_PI) +#if !CONFIG(CPU_AMD_PI) /* TODO: With binaryPI we need different interface. */ AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock); AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock); @@ -89,18 +89,18 @@ void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); -#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) +#if CONFIG(CPU_AMD_PI_00660F01) typedef void AMD_S3SAVE_PARAMS; #endif void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ #define HAS_AGESA_FCH_OEM_CALLOUT \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) + CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ + CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #if HAS_AGESA_FCH_OEM_CALLOUT /* FIXME: Structures included here were supposed to be private to AGESA. */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 405a7009bc..5090352e9a 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -22,7 +22,7 @@ void print_debug_addr(const char *str, void *val) { -#if IS_ENABLED(CONFIG_DEBUG_CAR) +#if CONFIG(DEBUG_CAR) printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } @@ -206,7 +206,7 @@ void dump_pci_devices_on_bus(u32 busn) } } -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl) { int i; @@ -300,17 +300,17 @@ void dump_io_resources(u32 port) } } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void print_tx(const char *strval, u32 val) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } void print_t(const char *strval) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s", strval); #endif } @@ -318,7 +318,7 @@ void print_t(const char *strval) void print_tf(const char *func, const char *strval) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s: %s", func, strval); #endif } diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a23303ebfa..3710d15b77 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -32,7 +32,7 @@ void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); void dump_pci_devices(void); void dump_pci_devices_on_bus(u32 busn); -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); #endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index afa07bb4d3..d8784ac728 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -22,7 +22,7 @@ // mmconf is not ready yet void set_bsp_node_CHtExtNodeCfgEn(void) { -#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT) +#if CONFIG(EXT_RT_TBL_SUPPORT) u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index f82f238bc0..871a4366c2 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -74,7 +74,7 @@ static void nb_control_init(struct device *dev) enable_c_states = 0; enable_cc6 = 0; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) uint8_t nvram; if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 8323c1e20f..bbaec53887 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -153,7 +153,7 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); -#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) +#if CONFIG(DIMM_DDR3) && !CONFIG(NORTHBRIDGE_AMD_AGESA) uint8_t node; uint8_t slot; uint8_t dimm_present; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index d202cd89bd..16b7becccc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -35,7 +35,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) #include <cpu/amd/multicore.h> #include <pc80/mc146818rtc.h> #endif @@ -49,7 +49,7 @@ #include <cpu/amd/model_10xxx_rev.h> #endif -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #include "../amdmct/mct_ddr3/s3utils.h" #endif @@ -316,7 +316,7 @@ static void amdfam10_scan_chains(struct device *dev) { struct bus *link; -#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) +#if CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA) if (is_fam15h()) { uint8_t current_link_number = 0; @@ -361,7 +361,7 @@ static void amdfam10_scan_chains(struct device *dev) for (link = dev->link_list; link; link = link->next) { if (link->ht_link_up) { - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) amd_g34_fixup(link, dev); amdfam10_scan_chain(link); } @@ -581,7 +581,7 @@ static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -640,7 +640,7 @@ static void mcf0_control_init(struct device *dev) { } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *amdfam10_northbridge_acpi_name(const struct device *dev) { return ""; @@ -653,7 +653,7 @@ static struct device_operations northbridge_operations = { .enable_resources = pci_dev_enable_resources, .init = mcf0_control_init, .scan_bus = amdfam10_scan_chains, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = northbridge_acpi_write_vars, .acpi_name = amdfam10_northbridge_acpi_name, @@ -886,7 +886,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) uint32_t topmem = (uint32_t) bsp_topmem(); uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ @@ -985,7 +985,7 @@ static void amdfam10_domain_set_resources(struct device *dev) i, mmio_basek, basek, limitk); } -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif @@ -1035,7 +1035,7 @@ static void amdfam10_domain_scan_bus(struct device *dev) } } -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int amdfam10_get_smbios_data16(int *count, int handle, unsigned long *current) { @@ -1085,7 +1085,7 @@ static int amdfam10_get_smbios_data16(int *count, int handle, static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) { if (is_fam15h()) { - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { switch (speed) { case 0x4: return 333; @@ -1106,7 +1106,7 @@ static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) return 0; } } else { - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + if (CONFIG(DIMM_DDR2)) { switch (speed) { case 1: return 200; @@ -1121,7 +1121,7 @@ static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) default: return 0; } - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + } else if (CONFIG(DIMM_DDR3)) { switch (speed) { case 3: return 333; @@ -1185,7 +1185,7 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, cols = mem_info->dct_stat[node].DimmCols[slot]; ranks = mem_info->dct_stat[node].DimmRanks[slot]; banks = mem_info->dct_stat[node].DimmBanks[slot]; -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) chip_size = mem_info->dct_stat[node].DimmChipSize[slot]; chip_width = mem_info->dct_stat[node].DimmChipWidth[slot]; #else @@ -1193,7 +1193,7 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, chip_width = 0; #endif uint64_t dimm_size_bytes; - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { width = mem_info->dct_stat[node].DimmWidth[slot]; dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8; } else { @@ -1226,9 +1226,9 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); } t->device_locator = smbios_add_string(t->eos, string_buffer); - if (IS_ENABLED(CONFIG_DIMM_DDR2)) + if (CONFIG(DIMM_DDR2)) t->memory_type = MEMORY_TYPE_DDR2; - else if (IS_ENABLED(CONFIG_DIMM_DDR3)) + else if (CONFIG(DIMM_DDR3)) t->memory_type = MEMORY_TYPE_DDR3; t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; if (mem_info->dct_stat[node].DimmRegistered[slot]) @@ -1245,13 +1245,13 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); t->serial_number = smbios_add_string(t->eos, string_buffer); } - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + if (CONFIG(DIMM_DDR2)) { /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */ t->minimum_voltage = 1800; t->maximum_voltage = 1800; t->configured_voltage = 1800; - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { -#if IS_ENABLED(CONFIG_DIMM_DDR3) + } else if (CONFIG(DIMM_DDR3)) { +#if CONFIG(DIMM_DDR3) /* Find the maximum and minimum supported voltages */ uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot]; uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot]; @@ -1308,7 +1308,7 @@ static int amdfam10_get_smbios_data(struct device *dev, int *handle, unsigned lo } #endif -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *amdfam10_domain_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -1324,10 +1324,10 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = amdfam10_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = amdfam10_domain_acpi_name, #endif -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = amdfam10_get_smbios_data, #endif }; @@ -1356,7 +1356,7 @@ static void sysconf_init(struct device *dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; @@ -1451,7 +1451,7 @@ static void cpu_bus_scan(struct device *dev) } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif @@ -1656,7 +1656,7 @@ static void cpu_bus_scan(struct device *dev) } } -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; @@ -1978,7 +1978,7 @@ static void root_complex_enable_dev(struct device *dev) } static void root_complex_finalize(void *chip_info) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(HAVE_ACPI_RESUME) && CONFIG(DIMM_DDR3) save_mct_information_to_nvram(); #endif } diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 8dee9ab814..4f31a5e848 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -150,8 +150,8 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi uint8_t MaxDimmsInstallable = 2; /* Return limited maximum RAM frequency */ - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_DDR2)) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 53 */ if (count > 2) { /* Limit to DDR2-533 */ @@ -170,7 +170,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi } } } - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + } else if (CONFIG(DIMM_DDR3)) { if (voltage == 0) { printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); voltage = 0x1; @@ -179,7 +179,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi if (is_fam15h()) { if (CONFIG_CPU_SOCKET_TYPE == 0x15) { /* Socket G34 */ - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* Fam15h BKDG Rev. 3.14 Table 27 */ if (voltage & 0x4) { /* 1.25V */ @@ -317,7 +317,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi } } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { /* Socket C32 */ - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* Fam15h BKDG Rev. 3.14 Table 30 */ if (voltage & 0x4) { /* 1.25V */ @@ -486,7 +486,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi */ } } else { - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 34 */ if (count > 2) { /* Limit to DDR3-800 */ @@ -548,7 +548,7 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) u8 mctGetProcessorPackageType(void) { /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ u32 BrandId = cpuid_ebx(0x80000001); @@ -601,7 +601,7 @@ void amdmct_cbmem_store_info(struct sys_info *sysinfo) mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); /* Zero out invalid/unused pointers */ -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) for (i = 0; i < MAX_NODES_SUPPORTED; i++) { mem_info->dct_stat[i].C_MCTPtr = NULL; mem_info->dct_stat[i].C_DCTPtr[0] = NULL; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index f919335360..8c33ad8156 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1489,13 +1489,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8) +#if CONFIG(LIMIT_HT_DOWN_WIDTH_8) cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8) +#if CONFIG(LIMIT_HT_UP_WIDTH_8) cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 6552be9532..bad8993395 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -272,7 +272,7 @@ void amd_ht_init(struct sys_info *sysinfo) */ void amd_ht_fixup(struct sys_info *sysinfo) { printk(BIOS_DEBUG, "%s\n", __func__); - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) { + if (CONFIG(CPU_AMD_MODEL_10XXX)) { uint8_t rev_gte_d = 0; uint8_t fam15h = 0; uint8_t dual_node = 0; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6f09b12a8a..9178c782d4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2620,7 +2620,7 @@ restartinit: mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -2692,11 +2692,11 @@ restartinit: nvram = 0; set_option("allow_spd_nvram_cache_restore", &nvram); -#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT) +#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif - if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) { + if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) { /* Assume 1.5V operation */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; @@ -3674,7 +3674,7 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); if (restore_mct_information_from_nvram(1) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -5836,7 +5836,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { @@ -5853,7 +5853,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) allow_config_restore = 0; #else diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 7267f12000..a78a752052 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -536,7 +536,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); for (i = 0; i < 12; i++) @@ -654,7 +654,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); for (i = 0; i < 12; i++) @@ -1093,7 +1093,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste } /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (node = 0; node < MAX_NODES_SUPPORTED; node++) { for (channel = 0; channel < 2; channel++) { struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index db92fa789e..92dc0b853c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -56,7 +56,7 @@ UPDATE AS NEEDED #endif #ifndef MAX_DIMMS_SUPPORTED -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MAX_DIMMS_SUPPORTED 6 #else #define MAX_DIMMS_SUPPORTED 8 @@ -72,7 +72,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 @@ -112,13 +112,13 @@ UPDATE AS NEEDED static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #include <northbridge/amd/amdmct/mct_ddr3/mct_d.h> #else #include <northbridge/amd/amdmct/mct/mct_d.h> #endif -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void); void mctGetDQSSigTmg_D(void); u8 mctSetNodeBoundary_D(void); @@ -144,7 +144,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc void mctHookAfterAnyTraining(void); uint64_t mctGetLogicalCPUID_D(u8 node); -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat); void vErratum414(struct DCTStatStruc *pDCTstat); u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b7d24764ed..e42085dce5 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -102,9 +102,9 @@ u16 mctGet_NVbits(u8 index) if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) { int limit = val; - if (IS_ENABLED(CONFIG_DIMM_DDR3)) + if (CONFIG(DIMM_DDR3)) limit = ddr3_limits[nvram & 0xf]; - else if (IS_ENABLED(CONFIG_DIMM_DDR2)) + else if (CONFIG(DIMM_DDR2)) limit = ddr2_limits[nvram & 0x3]; val = min(limit, val); } @@ -130,16 +130,16 @@ u16 mctGet_NVbits(u8 index) //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 4; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 7; #endif break; case NV_RDWRQBYP: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 2; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 3; #endif break; @@ -193,9 +193,9 @@ u16 mctGet_NVbits(u8 index) val = !!nvram; break; case NV_BurstLen32: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 0; /* 64 byte mode */ -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 1; /* 32 byte mode */ #endif break; @@ -214,9 +214,9 @@ u16 mctGet_NVbits(u8 index) case NV_BottomIO: case NV_BottomUMA: /* address bits [31:24] */ -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = (CONFIG_MMCONF_BASE_ADDRESS >> 24); -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G)) #error "MMCONF_BASE_ADDRESS is too small" #endif @@ -360,12 +360,12 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) if (pDCTstat->DimmRegistered[i + 1]) ch2_registered = 1; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) { + if (CONFIG(DEBUG_RAM_SETUP)) { printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count); printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; @@ -421,7 +421,7 @@ void mctHookAfterCPU(void) } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void) { } @@ -470,7 +470,7 @@ void mctHookAfterDramInit(void) { } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -504,7 +504,7 @@ void vErratum414(struct DCTStatStruc *pDCTstat) void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -513,7 +513,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc #endif } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { @@ -534,7 +534,7 @@ uint64_t mctGetLogicalCPUID_D(u8 node) return mctGetLogicalCPUID(node); } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) u8 mctSetNodeBoundary_D(void) { return 0; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index c24fb2d1b2..3f86427a8e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -36,7 +36,7 @@ #include <assert.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -370,7 +370,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -611,7 +611,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 19fb81415e..bf7c59adfd 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -35,7 +35,7 @@ #include <arch/acpigen.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -355,7 +355,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -610,7 +610,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) AGESAWRAPPER(amdinitmid); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9bbb2debc2..eb38c428f5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -37,7 +37,7 @@ #include <arch/acpigen.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -371,7 +371,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -843,7 +843,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) AGESAWRAPPER(amdinitmid); diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index b05c12012e..28f2876e95 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -55,8 +55,8 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)) + AmdResetParams.FchInterface.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) AmdResetParams.FchInterface.Xhci1Enable = TRUE; AmdResetParams.FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); @@ -96,7 +96,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) * init_timer() needs to be called on CZ PI, because AGESA resets the LAPIC reload value * on the AMD_INIT_EARLY call */ - if (IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01)) + if (CONFIG(CPU_AMD_PI_00660F01)) init_timer(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); @@ -299,7 +299,7 @@ const void *agesawrapper_locate_module (const CHAR8 name[8]) const AMD_MODULE_HEADER* module; size_t file_size; - if (IS_ENABLED(CONFIG_VBOOT)) { + if (CONFIG(VBOOT)) { /* Use phys. location in flash and prevent vboot from searching cbmem */ agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; file_size = 0x100000; diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index e5971d845f..e1cec43c32 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -16,7 +16,7 @@ #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <stdint.h> #include <Porting.h> @@ -51,7 +51,7 @@ static inline int agesawrapper_amds3laterestore(void) { return -1; } #endif -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) const void *agesawrapper_locate_module (const CHAR8 name[8]); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); |