7 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
index 079625671a..7668a089a6 100644
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ b/src/northbridge/amd/agesa/agesawrapper.c
@@ -111,7 +111,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	status = AmdInitPost(PostParams);
 	AGESA_EVENTLOG(status, &PostParams->StdHeader);
 
-	backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop);
+	backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);
 
 	AmdReleaseStruct(&AmdParamStruct);
 
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 02d5560d12..c957af0095 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -999,10 +999,10 @@ static void amdk8_domain_set_resources(device_t dev)
 	}
 
 #if CONFIG_GFXUMA
-	set_top_of_ram(uma_memory_base);
+	set_late_cbmem_top(uma_memory_base);
 	uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
 #else
-	set_top_of_ram(ramtop);
+	set_late_cbmem_top(ramtop);
 #endif
 	assign_resources(dev->link_list);
 
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 5c49f1add3..ef3b30a80d 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -286,7 +286,7 @@ static void pci_domain_set_resources(device_t dev)
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tomk - 768);	/* Systop - 0xc0000 -> KB */
 
-		set_top_of_ram(tomk * 1024);
+		set_late_cbmem_top(tomk * 1024);
 	}
 
 	assign_resources(dev->link_list);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index f0304becef..93ec3502e0 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -358,14 +358,14 @@ static void pci_domain_set_resources(device_t dev)
 
 	mc_dev = dev->link_list->children;
 	if (mc_dev) {
-		tomk = get_top_of_ram() / 1024;
+		tomk = restore_top_of_low_cacheable() / 1024;
 		/* Report the memory regions
 		   All memory up to systop except 0xa0000-0xbffff */
 		idx = 10;
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tomk - 768);	// Systop - 0xc0000 -> KB
 
-		set_top_of_ram(tomk * 1024);
+		set_late_cbmem_top(tomk * 1024);
 	}
 
 	assign_resources(dev->link_list);
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 6c48fb4155..f588ead56a 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -710,7 +710,7 @@ static void setup_lx_cache(void)
 	wbinvd();
 }
 
-unsigned long get_top_of_ram(void)
+uintptr_t restore_top_of_low_cacheable(void)
 {
 	uint32_t systop;
 	msr_t msr;
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index ec1d0acf9f..d4b9984f81 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -153,9 +153,9 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	 * UMA may or may not be cacheable, so Sub4GCacheTop could be
 	 * higher than UmaBase. With UMA_NONE we see UmaBase==0. */
 	if (PostParams->MemConfig.UmaBase)
-		backup_top_of_ram(PostParams->MemConfig.UmaBase << 16);
+		backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16);
 	else
-		backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop);
+		backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);
 
 	printk(
 			BIOS_SPEW,
diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c
index 2b501dcf05..8fa81c715a 100644
--- a/src/northbridge/amd/pi/ramtop.c
+++ b/src/northbridge/amd/pi/ramtop.c
@@ -19,13 +19,13 @@
 
 #define CBMEM_TOP_SCRATCHPAD 0x78
 
-void backup_top_of_ram(uint64_t ramtop)
+void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
 	uint16_t top_cache = ramtop >> 16;
 	pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache);
 }
 
-unsigned long get_top_of_ram(void)
+uintptr_t restore_top_of_low_cacheable(void)
 {
 	uint16_t top_cache;
 	top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);