3 files changed, 25 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8d85061f98..905d980f95 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -133,6 +133,23 @@ static void disable_probes(void)
 
 }
 
+#ifndef ENABLE_APIC_EXT_ID
+#define ENABLE_APIC_EXT_ID 0 
+#endif
+
+static void enable_apic_ext_id(u8 node)
+{
+#if ENABLE_APIC_EXT_ID==1
+#warning "FIXME Is the right place to enable apic ext id here?"
+
+        u32 val;
+
+        val = pci_read_config32(NODE_HT(node), 0x68);
+        val |= HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST ;
+        pci_write_config32(NODE_HT(node), 0x68, val);
+#endif
+}
+
 static void enable_routing(u8 node)
 {
 	u32 val;
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 40c18a6b95..b94a674ba8 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -715,6 +715,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 {
 	struct bus *cpu_bus;
 	int i;
+	int apic_id_offset = lapicid(); // bsp apicid
 
 	/* Find which cpus are present */
 	cpu_bus = &dev->link[0];
@@ -749,6 +750,9 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 		
 		/* Report what I have done */
 		if (cpu) {
+                        if(cpu->path.u.apic.apic_id<apic_id_offset) {
+                                cpu->path.u.apic.apic_id += apic_id_offset;
+                        }  
 			printk_debug("CPU: %s %s\n", dev_path(cpu),
 				     cpu->enabled?"enabled":"disabled");
 		}
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index 0663967b07..e60447c2ff 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -7,12 +7,12 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static int cpu_init_detected(void)
+static int cpu_init_detected(unsigned nodeid)
 {
 	unsigned long htic;
 	device_t dev;
 
-	dev = PCI_DEV(0, 0x18 + lapicid(), 0);
+	dev = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(dev, HT_INIT_CONTROL);
 
 	return !!(htic & HTIC_INIT_Detect);
@@ -34,11 +34,11 @@ static int cold_reset_detected(void)
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static void distinguish_cpu_resets(void)
+static void distinguish_cpu_resets(unsigned nodeid)
 {
 	uint32_t htic;
 	device_t device;
-	device = PCI_DEV(0, 0x18 + lapicid(), 0);
+	device = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(device, HT_INIT_CONTROL);
 	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
 	pci_write_config32(device, HT_INIT_CONTROL, htic);