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-rw-r--r--src/northbridge/amd/agesa/family12/dimmSpd.c2
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c4
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c2
4 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c
index 2f0af59c10..a0a1aea688 100644
--- a/src/northbridge/amd/agesa/family12/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family12/dimmSpd.c
@@ -55,7 +55,7 @@ AmdMemoryReadSPD (
IN UINT32 Func,
IN UINTN Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData
- )
+ )
{
UINT8 SmBusAddress = 0;
UINTN Index;
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index ae5b227bee..0a56d18e73 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -149,7 +149,7 @@ static struct resource *amdfam14_find_iopair(struct device *dev,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
- * but we need one index to differ them. So ,same node and same
+ * but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_io_addr_index(nodeid, link);
@@ -185,7 +185,7 @@ static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
- * but we need one index to differ them. So ,same node and same
+ * but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_mmio_addr_index(nodeid, link);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 2488dfc22b..91103ffb4f 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -1737,7 +1737,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
* and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3).
*/
- u8 ChipSel, Rows, Cols, Ranks ,Banks, DevWidth;
+ u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth;
u32 BankAddrReg, csMask;
u32 val;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index f62aa1568a..b62661b307 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -684,7 +684,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
- /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */
+ /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */
tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))