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-rw-r--r--src/northbridge/ibm/Kconfig2
-rw-r--r--src/northbridge/ibm/Makefile.inc2
-rw-r--r--src/northbridge/ibm/cpc710/Config.lb14
-rw-r--r--src/northbridge/ibm/cpc710/chip.h6
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.c92
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.h99
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_northbridge.c79
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_pci.c119
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_pci.h64
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_sdram.c12
-rw-r--r--src/northbridge/ibm/cpc925/Config.lb12
-rw-r--r--src/northbridge/ibm/cpc925/chip.h6
-rw-r--r--src/northbridge/ibm/cpc925/cpc925.c24
-rw-r--r--src/northbridge/ibm/cpc925/cpc925.h4
-rw-r--r--src/northbridge/ibm/cpc925/cpc925_northbridge.c79
-rw-r--r--src/northbridge/ibm/cpc925/cpc925_pci.c9
-rw-r--r--src/northbridge/ibm/cpc925/cpc925_pci.h4
17 files changed, 0 insertions, 627 deletions
diff --git a/src/northbridge/ibm/Kconfig b/src/northbridge/ibm/Kconfig
deleted file mode 100644
index 7f893b0ba0..0000000000
--- a/src/northbridge/ibm/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-#source src/northbridge/ibm/cpc710/Kconfig
-#source src/northbridge/ibm/cpc925/Kconfig
diff --git a/src/northbridge/ibm/Makefile.inc b/src/northbridge/ibm/Makefile.inc
deleted file mode 100644
index aebf07caa0..0000000000
--- a/src/northbridge/ibm/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-subdirs-y += cpc710
-subdirs-y += cpc925
diff --git a/src/northbridge/ibm/cpc710/Config.lb b/src/northbridge/ibm/cpc710/Config.lb
deleted file mode 100644
index 054a4c3997..0000000000
--- a/src/northbridge/ibm/cpc710/Config.lb
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Config file for IBM CPC710
-#
-
-config chip.h
-
-initobject cpc710.o
-initobject cpc710_pci.o
-#initobject cpc710_sdram.o
-
-object cpc710.o
-object cpc710_pci.o
-#object cpc710_sdram.o
-driver cpc710_northbridge.o
diff --git a/src/northbridge/ibm/cpc710/chip.h b/src/northbridge/ibm/cpc710/chip.h
deleted file mode 100644
index e2b2ed5eaa..0000000000
--- a/src/northbridge/ibm/cpc710/chip.h
+++ /dev/null
@@ -1,6 +0,0 @@
-
-struct northbridge_ibm_cpc710_config {
- /* Nothing yet */
-};
-
-extern struct chip_operations northbridge_ibm_cpc710_ops;
diff --git a/src/northbridge/ibm/cpc710/cpc710.c b/src/northbridge/ibm/cpc710/cpc710.c
deleted file mode 100644
index 8821850281..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710.c
+++ /dev/null
@@ -1,92 +0,0 @@
-#include <stdint.h>
-#include <arch/io.h>
-#include "cpc710.h"
-
-#define MCCR_DEFAULT \
- CPC710_MCCR_DIAG_MODE | \
- CPC710_MCCR_ECC_DISABLE | \
- CPC710_MCCR_REFRESH_7CY | \
- CPC710_MCCR_DATA_MASK | \
- CPC710_MCCR_FIXED_BITS
-
-void cpc710_init(void);
-void sdram_init(void);
-extern void cpc710_pci_init(void);
-
-void
-setCPC710(uint32_t addr, uint32_t data)
-{
- out_be32((unsigned *)(CPC710_PHYS_CPC0 + addr), data);
-}
-
-uint32_t
-getCPC710(uint32_t addr)
-{
- return (uint32_t)in_be32((unsigned *)(CPC710_PHYS_CPC0 + addr));
-}
-
-void
-memory_init(void)
-{
- cpc710_init();
- sdram_init();
- cpc710_pci_init();
-}
-
-void
-cpc710_init(void)
-{
- setCPC710(CPC710_CPC0_RSTR, 0xf0000000);
- (void)getCPC710(CPC710_CPC0_MPSR);
- setCPC710(CPC710_CPC0_SIOC0, 0x00000000);
- setCPC710(CPC710_CPC0_PIDR, 0x00000000);
- setCPC710(CPC710_CPC0_UCTL, 0x00780000);
- setCPC710(CPC710_CPC0_ABCNTL, 0x00000000);
- setCPC710(CPC710_CPC0_SRST, 0x00000000);
- setCPC710(CPC710_CPC0_ERRC, 0x00000000);
- setCPC710(CPC710_CPC0_SESR, 0x00000000);
- setCPC710(CPC710_CPC0_SEAR, 0x00000000);
- setCPC710(CPC710_CPC0_PGCHP, 0x000000e0);
- setCPC710(CPC710_CPC0_GPDIR, 0x40000000);
- setCPC710(CPC710_CPC0_GPOUT, 0x40000000);
- setCPC710(CPC710_CPC0_ATAS, 0x709c2508);
- setCPC710(CPC710_CPC0_AVDG, 0x00000000);
- setCPC710(CPC710_SDRAM0_MESR, 0x00000000);
- setCPC710(CPC710_SDRAM0_MEAR, 0x00000000);
- setCPC710(CPC710_SDRAM0_MWPR, 0x00000000);
- setCPC710(CPC710_CPC0_RGBAN1, 0x00000000);
-}
-
-void
-sdram_init()
-{
- uint32_t mccr;
-
- /*
- * Reset memory configuration
- */
- setCPC710(CPC710_SDRAM0_MCER0, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER1, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER2, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER3, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER4, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER5, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER6, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCER7, 0x00000000);
- setCPC710(CPC710_SDRAM0_MCCR, MCCR_DEFAULT);
-
- /*
- * Temoporarily configure memory. This will be
- * replaced by i2c later.
- */
- setCPC710(CPC710_SDRAM0_MCER0, 0x80000080);
- setCPC710(CPC710_SDRAM0_MCER1, 0x82000080);
- setCPC710(CPC710_SDRAM0_MCCR, 0xd2b06000);
-
- /*
- * wait for SDRAM init
- */
- do {
- mccr = getCPC710(CPC710_SDRAM0_MCCR);
- } while (mccr & CPC710_MCCR_INIT_STATUS != CPC710_MCCR_INIT_STATUS);
-}
diff --git a/src/northbridge/ibm/cpc710/cpc710.h b/src/northbridge/ibm/cpc710/cpc710.h
deleted file mode 100644
index ee5b413439..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPC710_H_
-#define _CPC710_H_
-
-/* Revision */
-#define CPC710_TYPE_100 0x80
-#define CPC710_TYPE_100P 0x90
-
-/* System control area */
-#define CPC710_PHYS_SCA 0xff000000
-
-#define CPC710_SCA_CPC0 0x000000
-#define CPC710_SCA_SDRAM0 0x000000
-#define CPC710_SCA_DMA0 0x1C0000
-
-#define CPC710_PHYS_CPC0 (CPC710_PHYS_SCA + CPC710_SCA_CPC0)
-#define CPC710_PHYS_SDRAM0 (CPC710_PHYS_SCA + CPC710_SCA_SDRAM0)
-
-#define CPC710_CPC0_PIDR 0x0008
-#define CPC710_CPC0_PCICNFR 0x000c
-#define CPC710_CPC0_RSTR 0x0010
-#define CPC710_CPC0_SPOR 0x00e8
-#define CPC710_CPC0_UCTL 0x1000
-#define CPC710_CPC0_MPSR 0x1010
-#define CPC710_CPC0_SIOC0 0x1020
-#define CPC710_CPC0_ABCNTL 0x1030
-#define CPC710_CPC0_SRST 0x1040
-#define CPC710_CPC0_ERRC 0x1050
-#define CPC710_CPC0_SESR 0x1060
-#define CPC710_CPC0_SEAR 0x1070
-#define CPC710_CPC0_PGCHP 0x1100
-#define CPC710_CPC0_RGBAN0 0x1110
-#define CPC710_CPC0_RGBAN1 0x1120
-
-#define CPC710_CPC0_GPDIR 0x1130
-#define CPC710_CPC0_GPIN 0x1140
-#define CPC710_CPC0_GPOUT 0x1150
-
-#define CPC710_CPC0_ATAS 0x1160
-#define CPC710_CPC0_AVDG 0x1170
-
-#define CPC710_CPC0_PCIBAR 0x200018
-#define CPC710_CPC0_PCIENB 0x201000
-
-#define CPC710_SDRAM0_MCCR 0x1200
-#define CPC710_SDRAM0_MWPR 0x1210
-#define CPC710_SDRAM0_MESR 0x1220
-#define CPC710_SDRAM0_MEAR 0x1230
-
-#define CPC710_SDRAM0_MCER0 0x1300
-#define CPC710_SDRAM0_MCER1 0x1310
-#define CPC710_SDRAM0_MCER2 0x1320
-#define CPC710_SDRAM0_MCER3 0x1330
-#define CPC710_SDRAM0_MCER4 0x1340
-#define CPC710_SDRAM0_MCER5 0x1350
-#define CPC710_SDRAM0_MCER6 0x1360
-#define CPC710_SDRAM0_MCER7 0x1370
-
-#define CPC710_SDRAM0_SIOR0 0x1400
-#define CPC710_SDRAM0_SIOR1 0x1420
-
-/* Configuration space registers */
-#define CPC710_BUS_NUMBER 0x40
-#define CPC710_SUB_BUS_NUMBER 0x41
-
-/* MCCR register bits */
-#define CPC710_MCCR_INIT_STATUS 0x20000000
-#define CPC710_MCCR_DIAG_MODE 0x40000000
-#define CPC710_MCCR_ECC_DISABLE 0x08000000
-#define CPC710_MCCR_REFRESH_7CY 0x02000000
-#define CPC710_MCCR_DATA_MASK 0x00100000
-#define CPC710_MCCR_FIXED_BITS 0x00008000
-
-extern void setCPC710(uint32_t, uint32_t);
-extern uint32_t getCPC710(uint32_t);
-
-#endif
diff --git a/src/northbridge/ibm/cpc710/cpc710_northbridge.c b/src/northbridge/ibm/cpc710/cpc710_northbridge.c
deleted file mode 100644
index 889080f4d3..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710_northbridge.c
+++ /dev/null
@@ -1,79 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include <cpu/cpu.h>
-#include "chip.h"
-
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void pci_domain_set_resources(device_t dev)
-{
- int idx;
-
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
-
- /* And assign the resources */
- assign_resources(&dev->link[0]);
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = &pci_ppc_conf1,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(&dev->link[0]);
-}
-
-static void cpu_bus_noop(device_t dev)
-{
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_ibm_cpc710_ops = {
- CHIP_NAME("IBM CPC710 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c
deleted file mode 100644
index 233e119baf..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710_pci.c
+++ /dev/null
@@ -1,119 +0,0 @@
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/pciconf.h>
-#include <delay.h>
-#include "cpc710.h"
-#include "cpc710_pci.h"
-
-extern void setCPC710(uint32_t, uint32_t);
-
-void
-setCPC710_PCI32(uint32_t addr, uint32_t data)
-{
- out_be32((unsigned *)(CPC710_PCI32_CONFIG + addr), data);
-}
-
-#if 0
-void
-setCPC710_PCI64(uint32_t addr, uint32_t data)
-{
- out_be32((unsigned *)(CPC710_PCI64_CONFIG + addr), data);
-}
-#endif
-
-void
-cpc710_pci_init(void)
-{
- /* Enable PCI32 */
- setCPC710(CPC710_CPC0_PCICNFR, 0x80000002); /* activate PCI32 config */
- setCPC710(CPC710_CPC0_PCIBAR, CPC710_PCI32_CONFIG); /* PCI32 base address */
- setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
- setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
-
- /* Reset PCI Status register */
- pci_ppc_write_config16(0, 0, 0x06, 0xffff);
-
- /* Configure bus number */
- pci_ppc_write_config16(0, 0, 0x40, 0);
-
- /* Set PCI configuration registers */
- setCPC710_PCI32(CPC710_PCIL0_PCIDG, 0x40000000);
- setCPC710_PCI32(CPC710_PCIL0_PIBAR, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_PMBAR, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_PR, 0xa000c000);
- setCPC710_PCI32(CPC710_PCIL0_ACR, 0xfc000000);
- setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE);
- setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE);
- setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE);
- setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE);
- setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080);
- setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_PSBAR, 0x00000080);
- setCPC710_PCI32(CPC710_PCIL0_BPMDLK, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_TPMDLK, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_BIODLK, 0x00000000);
- setCPC710_PCI32(CPC710_PCIL0_TIODLK, 0x00000000);
-
- /* Enable address space */
- pci_ppc_write_config16(0, 0, 0x04, 0xfda7);
-
- setCPC710_PCI32(CPC710_PCIL0_CRR, 0xfc000000);
-
- /*
- * wait for PCI to reset
- */
- udelay(250);
-
-#if 0
- /* Enable PCI64 */
- setCPC710(CPC710_CPC0_PCICNFR, 0x80000003); /* activate PCI64 config */
- setCPC710(CPC710_CPC0_PCIBAR, CPC710_PCI64_CONFIG); /* PCI64 base address */
- setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
- setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
-
- /* Reset PCI Status register */
- setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x06000080);
- setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xffff);
-
- /* Reset G_INT[A-D] bits in INT_RESET */
- setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x68000080);
- setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x0f000000);
-
- /* Configure bus number BUSNO=1, SUBNO=1 */
- setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x40000080);
- setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0x0101);
-
- /* Set PCI configuration registers */
- setCPC710_PCI64(CPC710_PCIL0_PSEA, 0x00000000);
- setCPC710_PCI64(CPC710_PCIL0_PCIDG, 0xc0000000);
- setCPC710_PCI64(CPC710_PCIL0_PIBAR, 0x00000000);
- setCPC710_PCI64(CPC710_PCIL0_PMBAR, 0x00000000);
- setCPC710_PCI64(CPC710_PCIL0_PR, 0x80008000);
- setCPC710_PCI64(CPC710_PCIL0_ACR, 0xff000000);
- setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE);
- setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE);
- setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE);
- setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE);
- setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000);
- setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080);
-
- /* Config PSBAR for PCI64 */
- setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x10000080);
- setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x00000080);
-
- setCPC710_PCI64(CPC710_PCIL0_BARPS, 0x00000000);
- setCPC710_PCI64(CPC710_PCIL0_INTSET, 0x00000000);
-
- /* Enable address space */
- setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x04000180);
- setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xfda7);
-
- setCPC710_PCI64(CPC710_PCIL0_CRR, 0xfc000000);
-
- /*
- * wait for PCI to reset
- */
- udelay(250);
-#endif
-}
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h
deleted file mode 100644
index a7f64dfcd8..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710_pci.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPC710_PCI_H_
-#define _CPC710_PCI_H_
-
-#define CPC710_PCI32_CONFIG (CONFIG_PCIC0_CFGADDR & 0xfff00000)
-#define CPC710_PCI32_MEM_SIZE 0xf8000000
-#define CPC710_PCI32_MEM_BASE 0xc0000000
-#define CPC710_PCI32_IO_SIZE 0xf8000000
-#define CPC710_PCI32_IO_BASE 0x80000000
-
-//#define CPC710_PCI64_CONFIG 0xff400000
-//#define CPC710_PCI64_MEM_SIZE 0xf8000000
-//#define CPC710_PCI64_MEM_BASE 0xc8000000
-//#define CPC710_PCI64_IO_SIZE 0xf8000000
-//#define CPC710_PCI64_IO_BASE 0x88000000
-
-#define CPC710_PCIL0_PSEA 0xf6110
-#define CPC710_PCIL0_PCIDG 0xf6120
-#define CPC710_PCIL0_INTACK 0xf7700
-#define CPC710_PCIL0_PIBAR 0xf7800
-#define CPC710_PCIL0_PMBAR 0xf7810
-#define CPC710_PCIL0_CRR 0xf7ef0
-#define CPC710_PCIL0_PR 0xf7f20
-#define CPC710_PCIL0_ACR 0xf7f30
-#define CPC710_PCIL0_MSIZE 0xf7f40
-#define CPC710_PCIL0_IOSIZE 0xf7f60
-#define CPC710_PCIL0_SMBAR 0xf7f80
-#define CPC710_PCIL0_SIBAR 0xf7fc0
-#define CPC710_PCIL0_CTLRW 0xf7fd0
-#define CPC710_PCIL0_CFGADDR 0xf8000 /* little endian */
-#define CPC710_PCIL0_CFGDATA 0xf8010 /* little endian */
-#define CPC710_PCIL0_PSSIZE 0xf8100
-#define CPC710_PCIL0_BARPS 0xf8120
-#define CPC710_PCIL0_PSBAR 0xf8140
-#define CPC710_PCIL0_BPMDLK 0xf8200
-#define CPC710_PCIL0_TPMDLK 0xf8210
-#define CPC710_PCIL0_BIODLK 0xf8220
-#define CPC710_PCIL0_TIODLK 0xf8230
-#define CPC710_PCIL0_INTSET 0xf8310
-
-
-#endif
diff --git a/src/northbridge/ibm/cpc710/cpc710_sdram.c b/src/northbridge/ibm/cpc710/cpc710_sdram.c
deleted file mode 100644
index e14463d749..0000000000
--- a/src/northbridge/ibm/cpc710/cpc710_sdram.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <mem.h>
-
-struct mem_range *
-sizeram(void)
-{
- static struct mem_range meminfo;
-
- meminfo.basek = 0;
- meminfo.sizek = 1024 * 1024; /* FIXME */
-
- return &meminfo;
-}
diff --git a/src/northbridge/ibm/cpc925/Config.lb b/src/northbridge/ibm/cpc925/Config.lb
deleted file mode 100644
index 8559c2e66a..0000000000
--- a/src/northbridge/ibm/cpc925/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Config file for IBM CPC925
-#
-
-config chip.h
-
-initobject cpc925.o
-initobject cpc925_pci.o
-
-object cpc925.o
-object cpc925_pci.o
-driver cpc925_northbridge.o
diff --git a/src/northbridge/ibm/cpc925/chip.h b/src/northbridge/ibm/cpc925/chip.h
deleted file mode 100644
index 1221bb3173..0000000000
--- a/src/northbridge/ibm/cpc925/chip.h
+++ /dev/null
@@ -1,6 +0,0 @@
-
-struct northbridge_ibm_cpc925_config {
- /* Nothing yet */
-};
-
-extern struct chip_operations northbridge_ibm_cpc925_ops;
diff --git a/src/northbridge/ibm/cpc925/cpc925.c b/src/northbridge/ibm/cpc925/cpc925.c
deleted file mode 100644
index 6bf126579a..0000000000
--- a/src/northbridge/ibm/cpc925/cpc925.c
+++ /dev/null
@@ -1,24 +0,0 @@
-#include <stdint.h>
-#include <arch/io.h>
-#include "cpc925.h"
-
-void cpc925_init(void);
-void sdram_init(void);
-
-void
-memory_init(void)
-{
- cpc925_init();
- sdram_init();
- cpc925_pci_init();
-}
-
-void
-cpc925_init(void)
-{
-}
-
-void
-sdram_init()
-{
-}
diff --git a/src/northbridge/ibm/cpc925/cpc925.h b/src/northbridge/ibm/cpc925/cpc925.h
deleted file mode 100644
index 2987f7d34e..0000000000
--- a/src/northbridge/ibm/cpc925/cpc925.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _CPC925_H_
-#define _CPC925_H_
-
-#endif
diff --git a/src/northbridge/ibm/cpc925/cpc925_northbridge.c b/src/northbridge/ibm/cpc925/cpc925_northbridge.c
deleted file mode 100644
index 6c5533d7b2..0000000000
--- a/src/northbridge/ibm/cpc925/cpc925_northbridge.c
+++ /dev/null
@@ -1,79 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include <cpu/cpu.h>
-#include "chip.h"
-
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void pci_domain_set_resources(device_t dev)
-{
- int idx;
-
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
-
- /* And assign the resources */
- assign_resources(&dev->link[0]);
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = &pci_ppc_conf1,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(&dev->link[0]);
-}
-
-static void cpu_bus_noop(device_t dev)
-{
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_ibm_cpc925_ops = {
- CHIP_NAME("IBM CPC925 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/ibm/cpc925/cpc925_pci.c b/src/northbridge/ibm/cpc925/cpc925_pci.c
deleted file mode 100644
index ae31685cad..0000000000
--- a/src/northbridge/ibm/cpc925/cpc925_pci.c
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <stdint.h>
-#include <arch/io.h>
-#include "cpc925.h"
-#include "cpc925_pci.h"
-
-void
-cpc925_pci_init(void)
-{
-}
diff --git a/src/northbridge/ibm/cpc925/cpc925_pci.h b/src/northbridge/ibm/cpc925/cpc925_pci.h
deleted file mode 100644
index 3415b2e057..0000000000
--- a/src/northbridge/ibm/cpc925/cpc925_pci.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _CPC925_PCI_H_
-#define _CPC925_PCI_H_
-
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 22:45:52 +0000